bsaleil updated this revision to Diff 277580.
bsaleil added a comment.
Herald added subscribers: llvm-commits, hiraditya.
Also add target options with this patch
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81442/new/
https://reviews.llvm.org/D81442
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -108,6 +108,7 @@
bool HasP10Vector;
bool HasPrefixInstrs;
bool HasPCRelativeMemops;
+ bool HasMMA;
bool HasFCPSGN;
bool HasFSQRT;
bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -267,6 +268,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool hasMMA() const { return HasMMA; }
bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,7 @@
HasP8Crypto = false;
HasP9Vector = false;
HasP9Altivec = false;
+ HasMMA = false;
HasP10Vector = false;
HasPrefixInstrs = false;
HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -43,8 +43,8 @@
// Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
// Engine), prefixed instructions on Power 9, PC relative mem ops, or
// instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops,
- PCRelativeMemops, IsISA3_1];
+ let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, MMA,
+ PairedVectorMemops, PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -428,6 +428,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
+def MMA : Predicate<"PPCSubTarget->hasMMA()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -241,6 +241,10 @@
SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
"32Byte load and store instructions",
[FeatureISA3_0]>;
+def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
+ "Enable MMA instructions",
+ [FeatureP8Vector, FeatureP9Altivec,
+ FeaturePairedVectorMemops]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -346,7 +350,8 @@
// still exist with the exception of those we know are Power9 specific.
list<SubtargetFeature> P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops];
+ FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
+ FeaturePairedVectorMemops];
list<SubtargetFeature> P10SpecificFeatures = [];
list<SubtargetFeature> P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Preprocessor/init-ppc64.c
===================================================================
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -643,6 +643,7 @@
// PPCPOWER10:#define _ARCH_PWR7 1
// PPCPOWER10:#define _ARCH_PWR8 1
// PPCPOWER10:#define _ARCH_PWR9 1
+// PPCPOWER10:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
//
@@ -660,6 +661,10 @@
// PPCFUTURE:#define _ARCH_PWR8 1
// PPCFUTURE:#define _ARCH_PWR9 1
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
+// PPCFUTURE:#define __MMA__ 1
+//
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
+// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
// PPC-FLOAT128:#define __FLOAT128__ 1
Index: clang/test/Driver/ppc-dependent-options.cpp
===================================================================
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -59,6 +59,14 @@
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-PAIRED-VEC-MEMOPS
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mmma %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=future -std=c++11 -mno-vsx -mmma %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
@@ -103,5 +111,6 @@
// CHECK-NVSX-PAIRED-VEC-MEMOPS: error: option '-mpaired-vector-memops' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-MMA: error: option '-mmma' cannot be specified with '-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
Index: clang/lib/Basic/Targets/PPC.h
===================================================================
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -59,6 +59,7 @@
// Target cpu features.
bool HasAltivec = false;
+ bool HasMMA = false;
bool HasVSX = false;
bool HasP8Vector = false;
bool HasP8Crypto = false;
Index: clang/lib/Basic/Targets/PPC.cpp
===================================================================
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -66,6 +66,8 @@
FloatABI = SoftFloat;
} else if (Feature == "+paired-vector-memops") {
PairedVectorMemops = true;
+ } else if (Feature == "+mma") {
+ HasMMA = true;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@@ -197,6 +199,8 @@
Builder.defineMacro("__FLOAT128__");
if (HasP9Vector)
Builder.defineMacro("__POWER9_VECTOR__");
+ if (HasMMA)
+ Builder.defineMacro("__MMA__");
if (HasP10Vector)
Builder.defineMacro("__POWER10_VECTOR__");
@@ -234,6 +238,7 @@
// - float128
// - power9-vector
// - paired-vector-memops
+// - mma
// - power10-vector
// then go ahead and error since the customer has expressed an incompatible
// set of options.
@@ -257,6 +262,7 @@
Found |= FindVSXSubfeature("+float128", "-mfloat128");
Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops");
+ Found |= FindVSXSubfeature("+mma", "-mmma");
Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
// Return false if any vsx subfeatures was found.
@@ -359,6 +365,7 @@
llvm::StringMap<bool> &Features) const {
Features["htm"] = false; // HTM was removed for P10.
Features["paired-vector-memops"] = true;
+ Features["mma"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
return;
@@ -388,6 +395,7 @@
.Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
+ .Case("mma", HasMMA)
.Default(false);
}
@@ -404,6 +412,7 @@
.Case("paired-vector-memops", true)
.Case("power10-vector", true)
.Case("float128", true)
+ .Case("mma", true)
.Default(false);
if (FeatureHasVSX)
Features["vsx"] = Features["altivec"] = true;
@@ -421,13 +430,14 @@
if ((Name == "altivec") || (Name == "vsx"))
Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
Features["float128"] = Features["power9-vector"] =
- Features["paired-vector-memops"] = Features["power10-vector"] =
- false;
+ Features["paired-vector-memops"] = Features["mma"] =
+ Features["power10-vector"] = false;
if (Name == "power8-vector")
Features["power9-vector"] = Features["paired-vector-memops"] =
- Features["power10-vector"] = false;
+ Features["mma"] = Features["power10-vector"] = false;
else if (Name == "power9-vector")
- Features["paired-vector-memops"] = Features["power10-vector"] = false;
+ Features["paired-vector-memops"] = Features["mma"] =
+ Features["power10-vector"] = false;
if (Name == "pcrel")
Features["pcrelative-memops"] = false;
else
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2469,6 +2469,8 @@
Group<m_ppc_Features_Group>;
def mno_longcall : Flag<["-"], "mno-longcall">,
Group<m_ppc_Features_Group>;
+def mmma: Flag<["-"], "mmma">, Group<m_ppc_Features_Group>;
+def mno_mma: Flag<["-"], "mno-mma">, Group<m_ppc_Features_Group>;
def maix_struct_return : Flag<["-"], "maix-struct-return">,
Group<m_Group>, Flags<[CC1Option]>,
HelpText<"Return all structs in memory (PPC32 only)">;
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