bsaleil updated this revision to Diff 281341.
bsaleil added a comment.
Update diff so it can be applied to master
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83722/new/
https://reviews.llvm.org/D83722
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() {
entry:
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -145,6 +145,7 @@
bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy;
+ bool PairedVectorMemops;
bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD;
@@ -259,6 +260,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -116,6 +116,7 @@
VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false;
+ PairedVectorMemops = false;
PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -41,8 +41,10 @@
let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on
- // Power 9, PC relative mem ops, or instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasSPE, PrefixInstrs, PCRelativeMemops, IsISA3_1];
+ // Power 9, paired vector mem ops, PC relative mem ops, or instructions
+ // introduced in ISA 3.1.
+ let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops,
+ PCRelativeMemops, IsISA3_1];
}
let SchedModel = P9Model in {
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -454,6 +454,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
+def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -234,6 +234,10 @@
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
[FeatureISA3_0]>;
+def FeaturePairedVectorMemops:
+ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
+ "32Byte load and store instructions",
+ [FeatureISA3_0]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -339,7 +343,7 @@
// still exist with the exception of those we know are Power9 specific.
list<SubtargetFeature> P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops, FeatureP10Vector];
+ FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops];
list<SubtargetFeature> P10SpecificFeatures = [];
list<SubtargetFeature> P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-dependent-options.cpp
===================================================================
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -54,6 +54,10 @@
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpaired-vector-memops %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-PAIRED-VEC-MEMOPS
+
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
@@ -96,6 +100,7 @@
// CHECK-NVSX-P10V: error: option '-mpower10-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX-FLT128: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-PAIRED-VEC-MEMOPS: error: option '-mpaired-vector-memops' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX: Neither enabled
Index: clang/lib/Basic/Targets/PPC.h
===================================================================
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -67,6 +67,7 @@
bool HasExtDiv = false;
bool HasP9Vector = false;
bool HasSPE = false;
+ bool PairedVectorMemops = false;
bool HasP10Vector = false;
bool HasPCRelativeMemops = false;
Index: clang/lib/Basic/Targets/PPC.cpp
===================================================================
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -62,6 +62,8 @@
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
} else if (Feature == "-hard-float") {
FloatABI = SoftFloat;
+ } else if (Feature == "+paired-vector-memops") {
+ PairedVectorMemops = true;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@@ -218,6 +220,7 @@
// - direct-move
// - float128
// - power9-vector
+// - paired-vector-memops
// - power10-vector
// then go ahead and error since the customer has expressed an incompatible
// set of options.
@@ -240,6 +243,7 @@
Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
Found |= FindVSXSubfeature("+float128", "-mfloat128");
Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
+ Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops");
Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
// Return false if any vsx subfeatures was found.
@@ -340,6 +344,7 @@
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap<bool> &Features) const {
Features["htm"] = false; // HTM was removed for P10.
+ Features["paired-vector-memops"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
return;
@@ -364,6 +369,7 @@
.Case("extdiv", HasExtDiv)
.Case("float128", HasFloat128)
.Case("power9-vector", HasP9Vector)
+ .Case("paired-vector-memops", PairedVectorMemops)
.Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
@@ -380,6 +386,7 @@
.Case("direct-move", true)
.Case("power8-vector", true)
.Case("power9-vector", true)
+ .Case("paired-vector-memops", true)
.Case("power10-vector", true)
.Case("float128", true)
.Default(false);
@@ -399,11 +406,13 @@
if ((Name == "altivec") || (Name == "vsx"))
Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
Features["float128"] = Features["power9-vector"] =
- Features["power10-vector"] = false;
+ Features["paired-vector-memops"] = Features["power10-vector"] =
+ false;
if (Name == "power8-vector")
- Features["power9-vector"] = Features["power10-vector"] = false;
+ Features["power9-vector"] = Features["paired-vector-memops"] =
+ Features["power10-vector"] = false;
else if (Name == "power9-vector")
- Features["power10-vector"] = false;
+ Features["paired-vector-memops"] = Features["power10-vector"] = false;
if (Name == "pcrel")
Features["pcrelative-memops"] = false;
else
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2453,6 +2453,10 @@
Group<m_ppc_Features_Group>;
def mnodirect_move : Flag<["-"], "mno-direct-move">,
Group<m_ppc_Features_Group>;
+def mpaired_vector_memops: Flag<["-"], "mpaired-vector-memops">,
+ Group<m_ppc_Features_Group>;
+def mnopaired_vector_memops: Flag<["-"], "mno-paired-vector-memops">,
+ Group<m_ppc_Features_Group>;
def mhtm : Flag<["-"], "mhtm">, Group<m_ppc_Features_Group>;
def mno_htm : Flag<["-"], "mno-htm">, Group<m_ppc_Features_Group>;
def mfprnd : Flag<["-"], "mfprnd">, Group<m_ppc_Features_Group>;
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