[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

[Baptiste Saleil via Phabricator via cfe-commits]

bsaleil added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:939
+  // The XFormMemOp flag for the following 8 insts is set on the instruction 
format.
+  let mayLoad = 1, mayStore = 1 in {
+    def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
----------------
Shouldn't `mayStore` be 0 instead of 1 here ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83364/new/

https://reviews.llvm.org/D83364



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