An array_reg is just a location in the register file with a size. It
will be used to pass around chunks of message payloads to transform
them in several ways and assemble them. The usual register types
aren't suitable for this because they don't carry size information,
and support complex addressing modes which aren't needed for this
purpose and unnecessarily increase the number of combinations we have
to handle.
As it doesn't know about align1 or align16 addressing modes, the same
type can be used in the VEC4 or FS backend, but it's necessary to
convert them to a "native" register type completing the missing
regioning information (width, swizzle, writemask, etc.) in order for
them to be usable with normal instructions.
---
src/mesa/drivers/dri/i965/brw_shader.h | 35 ++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index ac4e62a..df84cbd 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -138,6 +138,41 @@ struct backend_reg
bool abs;
};
+#ifdef __cplusplus
+
+/**
+ * A plain contiguous region of memory in your register file, with
+ * well-defined size and no fancy addressing modes, swizzling or striding.
+ */
+struct array_reg : public backend_reg {
+ array_reg() : backend_reg(), size(0)
+ {
+ }
+
+ explicit
+ array_reg(const backend_reg ®, unsigned size = 1) :
+ backend_reg(reg), size(size)
+ {
+ }
+
+ /** Size of the region in 32B registers. */
+ unsigned size;
+};
+
+/**
+ * Increase the register base offset by the specified amount given in
+ * 32B registers.
+ */
+inline array_reg
+offset(array_reg reg, unsigned delta)
+{
+ assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
+ reg.reg_offset += delta;
+ return reg;
+}
+
+#endif
+
struct cfg_t;
struct bblock_t;
--
2.3.5
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