It was far from obvious what unit the 'delta' argument is expressed in. --- src/mesa/drivers/dri/i965/brw_ir_fs.h | 5 +++++ src/mesa/drivers/dri/i965/brw_ir_svec4.h | 10 ++++++++++ src/mesa/drivers/dri/i965/brw_ir_vec4.h | 10 ++++++++++ 3 files changed, 25 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h index 676ed0d..e8c9cbc 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_fs.h +++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h @@ -169,6 +169,11 @@ horiz_offset(fs_reg reg, unsigned delta) return reg; } +/** + * Increase the register base offset by the specified amount given in units of + * the register width, which is one logical component for this IR (cf. + * fs_reg::traits::chan_size). + */ static inline fs_reg offset(fs_reg reg, unsigned delta) { diff --git a/src/mesa/drivers/dri/i965/brw_ir_svec4.h b/src/mesa/drivers/dri/i965/brw_ir_svec4.h index 90e0305..e023b9e 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_svec4.h +++ b/src/mesa/drivers/dri/i965/brw_ir_svec4.h @@ -142,6 +142,11 @@ namespace brw { return reg; } + /** + * Increase the register base offset by the specified amount given in units + * of the register width, which is one logical component for this IR (cf. + * src_svec4::traits::chan_size). + */ inline src_svec4 offset(const src_svec4 ®, unsigned delta) { @@ -292,6 +297,11 @@ namespace brw { return reg; } + /** + * Increase the register base offset by the specified amount given in units + * of the register width, which is one logical component for this IR (cf. + * dst_svec4::traits::chan_size). + */ inline dst_svec4 offset(const dst_svec4 ®, unsigned delta) { diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h index 4a79c57..e79f70f 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h @@ -99,6 +99,11 @@ retype(src_reg reg, enum brw_reg_type type) return reg; } +/** + * Increase the register base offset by the specified amount given in units of + * the register width, which is four logical components for this IR (cf. + * src_reg::traits::chan_size). + */ static inline src_reg offset(src_reg reg, unsigned delta) { @@ -225,6 +230,11 @@ retype(dst_reg reg, enum brw_reg_type type) return reg; } +/** + * Increase the register base offset by the specified amount given in units of + * the register width, which is four logical components for this IR (cf. + * dst_reg::traits::chan_size). + */ static inline dst_reg offset(dst_reg reg, unsigned delta) { -- 2.3.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev