Let's avoid confusion between vector components (i.e. semantically
different values, each in turn represented as a vector with a separate
value for each logical thread being executed in the same SIMD thread)
and channels (i.e. one of the N instances of some scalar value of the
program running in SIMD(Mx)N mode). component() was giving you the
latter. A future commit will introduce a proper component() helper
function with consistent behaviour across back-ends.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 17 ++++++++---------
src/mesa/drivers/dri/i965/brw_ir_fs.h | 23 +++++++++++++----------
3 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index bee8a54..b9eb561 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2544,8 +2544,8 @@ fs_visitor::opt_algebraic()
} else if (inst->src[1].file == IMM) {
inst->opcode = BRW_OPCODE_MOV;
- inst->src[0] = component(inst->src[0],
- inst->src[1].fixed_hw_reg.dw1.ud);
+ inst->src[0] = channel(inst->src[0],
+ inst->src[1].fixed_hw_reg.dw1.ud);
inst->sources = 1;
inst->force_writemask_all = true;
progress = true;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 9aff84d..0d4dd5a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -339,10 +339,9 @@ fs_visitor::emit_uniformize(const fs_reg &dst, const
fs_reg &src)
{
const fs_reg chan_index = vgrf(glsl_type::uint_type);
- emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, component(chan_index, 0))
+ emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, channel(chan_index, 0))
->force_writemask_all = true;
- emit(SHADER_OPCODE_BROADCAST, component(dst, 0),
- src, component(chan_index, 0))
+ emit(SHADER_OPCODE_BROADCAST, channel(dst, 0), src, channel(chan_index, 0))
->force_writemask_all = true;
}
@@ -3255,10 +3254,10 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op,
unsigned surf_index,
if (stage == MESA_SHADER_FRAGMENT) {
if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+ emit(MOV(channel(sources[0], 7), brw_flag_reg(0, 1)))
->force_writemask_all = true;
} else {
- emit(MOV(component(sources[0], 7),
+ emit(MOV(channel(sources[0], 7),
retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
->force_writemask_all = true;
}
@@ -3269,7 +3268,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op,
unsigned surf_index,
* the atomic operation.
*/
assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
- emit(MOV(component(sources[0], 7),
+ emit(MOV(channel(sources[0], 7),
fs_reg(0xffffu)))->force_writemask_all = true;
}
length++;
@@ -3318,10 +3317,10 @@ fs_visitor::emit_untyped_surface_read(unsigned
surf_index, fs_reg dst,
if (stage == MESA_SHADER_FRAGMENT) {
if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+ emit(MOV(channel(sources[0], 7), brw_flag_reg(0, 1)))
->force_writemask_all = true;
} else {
- emit(MOV(component(sources[0], 7),
+ emit(MOV(channel(sources[0], 7),
retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
->force_writemask_all = true;
}
@@ -3332,7 +3331,7 @@ fs_visitor::emit_untyped_surface_read(unsigned
surf_index, fs_reg dst,
* the atomic operation.
*/
assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
- emit(MOV(component(sources[0], 7),
+ emit(MOV(channel(sources[0], 7),
fs_reg(0xffffu)))->force_writemask_all = true;
}
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index e2d2617..e4ad657e 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -157,16 +157,6 @@ offset(fs_reg reg, unsigned delta)
return reg;
}
-static inline fs_reg
-component(fs_reg reg, unsigned idx)
-{
- assert(reg.subreg_offset == 0);
- assert(idx < reg.width);
- reg.subreg_offset = idx * type_sz(reg.type);
- reg.width = 1;
- return reg;
-}
-
static inline bool
is_uniform(const fs_reg ®)
{
@@ -193,6 +183,19 @@ half(fs_reg reg, unsigned idx)
return horiz_offset(reg, 8 * idx);
}
+/**
+ * Return the i-th SIMD channel of a register.
+ */
+static inline fs_reg
+channel(fs_reg reg, unsigned i)
+{
+ assert(reg.subreg_offset == 0);
+ assert(i < reg.width);
+ reg.subreg_offset = i * type_sz(reg.type);
+ reg.width = 1;
+ return reg;
+}
+
static const fs_reg reg_undef;
class fs_inst : public backend_instruction {
--
2.3.5
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