On Fri, 07 Aug 2026 09:46:03 +0200, Luca Weiss wrote:
> I've noticed that the .clk_cbcrs list in multiple clock drivers enable
> the GCC_PCIE_RSCC_CFG_AHB_CLK and GCC_PCIE_RSCC_XO_CLK wrongly.
>
> qcom_branch_set_clk_en() will be called on each entry which will set
> BIT(0) to enable the clock, but this is wrong for these two clocks which
> -- this is also why this is marked RFT -- at least for kaanapali
> needs BIT(20) and BIT(21) set to enable them.
>
> [...]
Applied, thanks!
[1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks
commit: 34e0ef622cd41eb5ee77d6aae79276c12de7c20f
[2/3] clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks
commit: c83e1427064e6fe95604b469f4c670e1839f409a
[3/3] clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks
commit: 7f6869e53f73c4ca0e622a6a1b5ac2598fee5931
Best regards,
--
Bjorn Andersson <[email protected]>
