[PATCH RFT 1/3] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks

[Luca Weiss]

The critical_cbrcrs array will get qcom_branch_set_clk_en() called on
each entry which will set BIT(0) to enable the clock. This is however
wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set
respectively to enable them.

Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on 
Eliza")
Signed-off-by: Luca Weiss <luca.we...@fairphone.com>
---
 drivers/clk/qcom/gcc-eliza.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c
index 3e26c7a1e5b5..fe18942a59ac 100644
--- a/drivers/clk/qcom/gcc-eliza.c
+++ b/drivers/clk/qcom/gcc-eliza.c
@@ -3010,8 +3010,6 @@ static const u32 gcc_eliza_critical_cbcrs[] = {
        0x26034, /* GCC_CAMERA_XO_CLK */
        0x27004, /* GCC_DISP_AHB_CLK */
        0x71004, /* GCC_GPU_CFG_AHB_CLK */
-       0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */
-       0x52010, /* GCC_PCIE_RSCC_XO_CLK */
        0x32004, /* GCC_VIDEO_AHB_CLK */
        0x32038, /* GCC_VIDEO_XO_CLK */
 };
@@ -3045,6 +3043,10 @@ static const struct regmap_config 
gcc_eliza_regmap_config = {
 
 static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)
 {
+       /* Keep clocks always enabled */
+       regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* 
GCC_PCIE_RSCC_CFG_AHB_CLK */
+       regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); /* 
GCC_PCIE_RSCC_XO_CLK */
+
        /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
        qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
        qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);

-- 
2.55.0