I've noticed that the .clk_cbcrs list in multiple clock drivers enable the GCC_PCIE_RSCC_CFG_AHB_CLK and GCC_PCIE_RSCC_XO_CLK wrongly.
qcom_branch_set_clk_en() will be called on each entry which will set BIT(0) to enable the clock, but this is wrong for these two clocks which -- this is also why this is marked RFT -- at least for kaanapali needs BIT(20) and BIT(21) set to enable them. I don't know which downstream codename (in the vendor kernel) eliza and hawi are so I just assumed the same BIT(20) and BIT(21) would be correct there. Please verify this! Signed-off-by: Luca Weiss <[email protected]> --- Luca Weiss (3): clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks clk: qcom: gcc-hawi: Fix always-enabling PCIE_RSCC clocks clk: qcom: gcc-kaanapali: Fix always-enabling PCIE_RSCC clocks drivers/clk/qcom/gcc-eliza.c | 6 ++++-- drivers/clk/qcom/gcc-hawi.c | 6 ++++-- drivers/clk/qcom/gcc-kaanapali.c | 6 ++++-- 3 files changed, 12 insertions(+), 6 deletions(-) --- base-commit: d56fa0b2bd2d9b2fddc10e8f5bdd42d56676935c change-id: 20260807-various-pcie-clk-fix-6bafb619e7ab Best regards, -- Luca Weiss <[email protected]>
