On 26-08-07 09:46:04, Luca Weiss wrote:
> The critical_cbrcrs array will get qcom_branch_set_clk_en() called on
> each entry which will set BIT(0) to enable the clock. This is however
> wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set
> respectively to enable them.
>
> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on
> Eliza")
> Signed-off-by: Luca Weiss <[email protected]>
Tested on CQS EVK, which does have PCIe endpoints.
Tested-by: Abel Vesa <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
