From: Ville Syrjälä <[email protected]> Restructure bits for VRR enablement.
--v2: - Separate multiple enablement from one patch. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Mitul Golani <[email protected]> Reviewed-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_vrr.c | 27 ++++++++++++------------ 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index b2348ae10a1a..88ac4d93586b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -603,6 +603,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 ctl; if (!crtc_state->vrr.enable) return; @@ -617,17 +618,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); - if (!intel_vrr_always_use_vrr_tg(display)) { - if (crtc_state->cmrr.enable) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | - trans_vrr_ctl(crtc_state)); - } else { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); - } - } - if (crtc_state->vrr.dc_balance.enable) { intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), crtc_state->vrr.dc_balance.vmin - 1); @@ -644,16 +634,29 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), crtc_state->vrr.dc_balance.vblank_target); } + + ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state); + if (crtc_state->cmrr.enable) + ctl |= VRR_CTL_CMRR_ENABLE; + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl); } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(old_crtc_state); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; + u32 ctl; if (!old_crtc_state->vrr.enable) return; + ctl = trans_vrr_ctl(old_crtc_state); + if (intel_vrr_always_use_vrr_tg(display)) + ctl |= VRR_CTL_VRR_ENABLE; + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl); + if (old_crtc_state->vrr.dc_balance.enable) { intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0); @@ -664,8 +667,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) } if (!intel_vrr_always_use_vrr_tg(display)) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(old_crtc_state)); intel_de_wait_for_clear(display, TRANS_VRR_STATUS(display, cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000); -- 2.48.1
