Configure PIPEDMC_EVT_CTL_3 register with required event flags.
Signed-off-by: Mitul Golani <[email protected]>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 20 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 11 +++++++++--
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 593f5140475b..077bb6bb0bb4 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -534,6 +534,26 @@ void intel_dmc_block_pkgc(struct intel_display *display,
enum pipe pipe,
PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0);
}
+void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
+ enum pipe pipe, bool enable)
+{
+ u32 val;
+
+ if (enable)
+ val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING |
+ REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+ DMC_EVT_CTL_TYPE_EDGE_0_1) |
+ REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+
DMC_EVT_CTL_EVENT_ID_ADAPTIVE_DC_BALANCE_TRIGGER);
+ else
+ val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
+ DMC_EVT_CTL_EVENT_ID_FALSE) |
+ REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
+ DMC_EVT_CTL_TYPE_EDGE_0_1);
+
+ intel_de_write(display, PIPEDMC_EVT_CTL_3(pipe), val);
+}
+
/**
* intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG
* C-state exit
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 48869f19079a..a998c3614e1c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -22,6 +22,8 @@ void intel_dmc_enable_pipe(struct intel_display *display,
enum pipe pipe);
void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe);
void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
bool block);
+void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
+ enum pipe pipe, bool enable);
void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct
intel_display *display,
enum pipe pipe,
bool enable);
void intel_dmc_fini(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index cd14d7efb863..5ca71df79430 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -620,7 +620,9 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
u32 ctl;
if (!crtc_state->vrr.enable)
@@ -659,22 +661,27 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
- if (crtc_state->vrr.dc_balance.enable)
+ if (crtc_state->vrr.dc_balance.enable) {
+ intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
intel_pipedmc_dcb_enable(NULL, crtc);
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_display *display = to_intel_display(old_crtc_state);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
u32 ctl;
if (!old_crtc_state->vrr.enable)
return;
- if (old_crtc_state->vrr.dc_balance.enable)
+ if (old_crtc_state->vrr.dc_balance.enable) {
intel_pipedmc_dcb_disable(NULL, crtc);
+ intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false);
+ }
ctl = trans_vrr_ctl(old_crtc_state);
if (intel_vrr_always_use_vrr_tg(display))
--
2.48.1
