Add VRR register offsets and bits to access DC Balance configuration. --v2: - Separate register definitions. (Ankit) - Remove usage of dev_priv. (Jani, Nikula)
--v3: - Convert register address offset, from capital to small. (Ankit) - Move mask bits near to register offsets. (Ankit) Co-authored-by: Mitul Golani <[email protected]> Signed-off-by: Mitul Golani <[email protected]> --- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 6ed0e0dc97e7..204d5b35bc4b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -9,6 +9,53 @@ #include "intel_display_reg_defs.h" /* VRR registers */ +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4 +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4 +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C 0x624d4 +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D 0x634d4 +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, \ + trans) _MMIO_TRANS2(display, trans, \ + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A) +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8 +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8 +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C 0x624d8 +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D 0x634d8 +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_VRR_DCB_ADJ_VMAX_CFG_A) +#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_FLIPLINE_DCB_A 0x60418 +#define _TRANS_VRR_FLIPLINE_DCB_B 0x61418 +#define _TRANS_VRR_FLIPLINE_DCB_C 0x62418 +#define _TRANS_VRR_FLIPLINE_DCB_D 0x63418 +#define TRANS_VRR_FLIPLINE_DCB(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_VRR_FLIPLINE_DCB_A) +#define VRR_FLIPLINE_DCB_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_VMAX_DCB_A 0x60414 +#define _TRANS_VRR_VMAX_DCB_B 0x61414 +#define _TRANS_VRR_VMAX_DCB_C 0x62414 +#define _TRANS_VRR_VMAX_DCB_D 0x63414 +#define TRANS_VRR_VMAX_DCB(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_VRR_VMAX_DCB_A) +#define VRR_VMAX_DCB_MASK REG_GENMASK(19, 0) + +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0 +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0 +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C 0x624c0 +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D 0x634c0 +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_ADAPTIVE_SYNC_DCB_CTL_A) +#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31) + #define _TRANS_VRR_CTL_A 0x60420 #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 @@ -20,6 +67,7 @@ #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) +#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28) #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) -- 2.48.1
