From: Ville Syrjälä <[email protected]> Pause the DMC DC Balancing for the remainder of the commit so that vmin/vmax won't change after we've baked them into the DSB vblank evasion commands.
--v2: - Remove typo. (Ankit) - Separate vrr enable structuring. (Ankit) --v3: - Add gaurd before accessing DC balance bits. - Remove redundancy checks. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Mitul Golani <[email protected]> Reviewed-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c06047a8bf1b..d1a2e694b6a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7217,6 +7217,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, } if (new_crtc_state->use_dsb) { + if (new_crtc_state->vrr.dc_balance.enable) { + /* + * Pause the DMC DC balancing for the remainder of + * the commit so that vmin/vmax won't change after + * we've baked them into the DSB vblank evasion + * commands. + * + * FIXME maybe need a small delay here to make sure + * DMC has finished updating the values? Or we need + * a better DMC<->driver protocol that gives is real + * guarantees about that... + */ + intel_pipedmc_dcb_disable(NULL, crtc); + } + if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_commit_noarm(new_crtc_state->dsb_commit, new_crtc_state); @@ -7253,6 +7268,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); + if (new_crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); intel_dsb_interrupt(new_crtc_state->dsb_commit); } } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 88ac4d93586b..3a5d29327d4d 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dp.h" #include "intel_dmc_regs.h" #include "intel_vrr.h" @@ -602,6 +603,7 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 ctl; @@ -640,17 +642,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) ctl |= VRR_CTL_CMRR_ENABLE; intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl); + + if (crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_enable(NULL, crtc); } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(old_crtc_state); + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; u32 ctl; if (!old_crtc_state->vrr.enable) return; + if (old_crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_disable(NULL, crtc); + ctl = trans_vrr_ctl(old_crtc_state); if (intel_vrr_always_use_vrr_tg(display)) ctl |= VRR_CTL_VRR_ENABLE; -- 2.48.1
