On Fri, 2009-01-09 at 01:22 -0500, DJ Delorie wrote:
> > I know you are very busy and its very difficult to discuss all the
> > details. Do you think an example, or a screen shot may help?
> 
> In my case, what I want is pretty simple to show.  I want these to be
> equivalent: http://www.delorie.com/pcb/djbus.png
> 
> The netlister backends should always see the "demultiplexed"
> connections.  I.e. they'll see the top net/pin connection as if you'd
> done the bottom set of connections.

Hi DJ,

I was thinking that buses could be more flexible than this.. only some
backends will want the flattened output. VHDL / Verilog can deal with
buses as native interconnections - and they might have more complex
data-types than an n-ary list of nets.

As step one, gnetlist can now (if enabled) netlist bus pins / buses
similarly to how it does nets and net pins. (They end up in the same
list, but tagged with their type - so we could teach existing back-ends
to ignore buses if we wanted).

Once we've thought about what flattening syntax we want, I propose we
write a shared .scm file, possibly with some C helpers for doing the
leg-work on the netlist, whereby the buses can be flattened and added to
the netlist much as nets currently can with netname= attributes.

Back-ends which care (or an opt-out for backends which wish to deal with
buses differently) can then share the same syntax and functionality.

For PCB, I think we need additional attributes (if footprint symbols
were to support bus pins), since we need a mapping onto pin-number for
each element in the bus). This would be similar to the "net=foo:1", but
with the "foo" scoped to search for named signals inside the symbol's
pins, rather than extending outside the scope of the symbol.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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