From: Abhishek Kaushik <[email protected]>
This patch adds support for following absolute difference accumulation
intrinsics defined by SVE/SME2.3
* svabal_s16
* svabal_n_s16
* svabal_s32
* svabal_n_s32
* svabal_s64
* svabal_n_s64
* svabal_u16
* svabal_n_u16
* svabal_u32
* svabal_n_u32
* svabal_u64
* svabal_n_u64
---
.../aarch64/aarch64-sve-builtins-sve2.cc | 2 +
.../aarch64/aarch64-sve-builtins-sve2.def | 1 +
.../aarch64/aarch64-sve-builtins-sve2.h | 1 +
gcc/config/aarch64/iterators.md | 18 +++-
.../aarch64/sve2/acle/asm/abal_s16.c | 88 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_s32.c | 88 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_s64.c | 88 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_u16.c | 88 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_u32.c | 88 +++++++++++++++++++
.../aarch64/sve2/acle/asm/abal_u64.c | 88 +++++++++++++++++++
10 files changed, 547 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
index 56f64fa0e37..477093f8d6a 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
@@ -1067,6 +1067,8 @@ public:
namespace aarch64_sve {
FUNCTION (svaba, svaba_impl,)
+FUNCTION (svabal, unspec_based_add_function, (UNSPEC_SABAL,
+ UNSPEC_UABAL, -1))
FUNCTION (svabalb, unspec_based_add_function, (UNSPEC_SABDLB,
UNSPEC_UABDLB, -1))
FUNCTION (svabalt, unspec_based_add_function, (UNSPEC_SABDLT,
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
index b77ccd06205..0dafcfed234 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
@@ -316,6 +316,7 @@ DEF_SVE_FUNCTION (svrint64z, unary, sd_float, mxz)
#undef REQUIRED_EXTENSIONS
#define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2p3, AARCH64_FL_SME2p3)
+DEF_SVE_FUNCTION (svabal, ternary_long_opt_n, hsd_integer, none)
DEF_SVE_FUNCTION (svdot, ternary_qq_opt_n_or_011, s_narrow_fsu_sve2p3, none)
DEF_SVE_FUNCTION (svdot_lane, ternary_qq_or_011_lane, s_narrow_fsu_sve2p3,
none)
DEF_SVE_FUNCTION_GS (svqrshrn, shift_right_imm_narrowxn, qrshr_x2_sve2p3, x2,
none)
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
index d2b193776c7..9c8660a11de 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
@@ -25,6 +25,7 @@ namespace aarch64_sve
namespace functions
{
extern const function_base *const svaba;
+ extern const function_base *const svabal;
extern const function_base *const svabalb;
extern const function_base *const svabalt;
extern const function_base *const svabdlb;
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 108c2f886d5..0ed0172be69 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -1211,6 +1211,7 @@ (define_c_enum "unspec"
UNSPEC_RSHRNT ; Used in aarch64-sve2.md.
UNSPEC_RSUBHNB ; Used in aarch64-sve2.md.
UNSPEC_RSUBHNT ; Used in aarch64-sve2.md.
+ UNSPEC_SABAL ; Used in aarch64-sve2.md.
UNSPEC_SABDLB ; Used in aarch64-sve2.md.
UNSPEC_SABDLT ; Used in aarch64-sve2.md.
UNSPEC_SADDLB ; Used in aarch64-sve2.md.
@@ -1271,6 +1272,7 @@ (define_c_enum "unspec"
UNSPEC_SUBHNT ; Used in aarch64-sve2.md.
UNSPEC_TBL2 ; Used in aarch64-sve2.md.
UNSPEC_TRN ; Used in aarch64-builtins.cc
+ UNSPEC_UABAL ; Used in aarch64-sve2.md.
UNSPEC_UABDLB ; Used in aarch64-sve2.md.
UNSPEC_UABDLT ; Used in aarch64-sve2.md.
UNSPEC_UADDLB ; Used in aarch64-sve2.md.
@@ -4025,7 +4027,8 @@ (define_int_iterator SVE2_INT_BINARY [UNSPEC_SQDMULH
(define_int_iterator SVE2_INT_BINARY_LANE [UNSPEC_SQDMULH
UNSPEC_SQRDMULH])
-(define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABDLB
+(define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABAL
+ UNSPEC_SABDLB
UNSPEC_SABDLT
UNSPEC_SADDLB
UNSPEC_SADDLBT
@@ -4038,6 +4041,7 @@ (define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABDLB
UNSPEC_SSUBLBT
UNSPEC_SSUBLT
UNSPEC_SSUBLTB
+ UNSPEC_UABAL
UNSPEC_UABDLB
UNSPEC_UABDLT
UNSPEC_UADDLB
@@ -4184,10 +4188,12 @@ (define_int_iterator SVE2_INT_CDOT [UNSPEC_CDOT
UNSPEC_CDOT180
UNSPEC_CDOT270])
-(define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABDLB
+(define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABAL
+ UNSPEC_SABDLB
UNSPEC_SABDLT
UNSPEC_SMULLB
UNSPEC_SMULLT
+ UNSPEC_UABAL
UNSPEC_UABDLB
UNSPEC_UABDLT
UNSPEC_UMULLB
@@ -5000,6 +5006,7 @@ (define_int_attr sve_int_op [(UNSPEC_ADCLB "adclb")
(UNSPEC_RSQRTE "ursqrte")
(UNSPEC_RSUBHNB "rsubhnb")
(UNSPEC_RSUBHNT "rsubhnt")
+ (UNSPEC_SABAL "sabal")
(UNSPEC_SABDLB "sabdlb")
(UNSPEC_SABDLT "sabdlt")
(UNSPEC_SADALP "sadalp")
@@ -5071,6 +5078,7 @@ (define_int_attr sve_int_op [(UNSPEC_ADCLB "adclb")
(UNSPEC_SUBHNB "subhnb")
(UNSPEC_SUBHNT "subhnt")
(UNSPEC_SUQADD "suqadd")
+ (UNSPEC_UABAL "uabal")
(UNSPEC_UABDLB "uabdlb")
(UNSPEC_UABDLT "uabdlt")
(UNSPEC_UADALP "uadalp")
@@ -5122,10 +5130,12 @@ (define_int_attr sve_int_op_rev [(UNSPEC_SHADD "shadd")
(UNSPEC_URHADD "urhadd")
(UNSPEC_URSHL "urshlr")])
-(define_int_attr sve_int_add_op [(UNSPEC_SABDLB "sabalb")
+(define_int_attr sve_int_add_op [(UNSPEC_SABAL "sabal")
+ (UNSPEC_SABDLB "sabalb")
(UNSPEC_SABDLT "sabalt")
(UNSPEC_SMULLB "smlalb")
(UNSPEC_SMULLT "smlalt")
+ (UNSPEC_UABAL "uabal")
(UNSPEC_UABDLB "uabalb")
(UNSPEC_UABDLT "uabalt")
(UNSPEC_UMULLB "umlalb")
@@ -5190,6 +5200,7 @@ (define_int_attr sve_type_unspec [(UNSPEC_COND_FABS
"fp_arith")
(UNSPEC_SBCLT "int_general")
(UNSPEC_SQRDMLAH "int_mul")
(UNSPEC_SQRDMLSH "int_mul")
+ (UNSPEC_SABAL "int_general")
(UNSPEC_SABDLB "int_general")
(UNSPEC_SABDLT "int_general")
(UNSPEC_SADDLB "int_general")
@@ -5204,6 +5215,7 @@ (define_int_attr sve_type_unspec [(UNSPEC_COND_FABS
"fp_arith")
(UNSPEC_SSUBLBT "int_general")
(UNSPEC_SSUBLT "int_general")
(UNSPEC_SSUBLTB "int_general")
+ (UNSPEC_UABAL "int_general")
(UNSPEC_UABDLB "int_general")
(UNSPEC_UABDLT "int_general")
(UNSPEC_UADDLB "int_general")
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
new file mode 100644
index 00000000000..d64c63f6270
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s16.c
@@ -0,0 +1,88 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_s16_tied1:
+** sabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_s16_tied1, svint16_t, svint8_t,
+ z0 = svabal_s16 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_s16_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.h, \1\.b, z1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s16_tied2, svint16_t, svint8_t,
+ z0_res = svabal_s16 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_s16_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.h, z1\.b, \1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s16_tied3, svint16_t, svint8_t,
+ z0_res = svabal_s16 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_s16_untied:
+** movprfx z0, z1
+** sabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_s16_untied, svint16_t, svint8_t,
+ z0 = svabal_s16 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_s16_tied1:
+** mov (z[0-9]+\.b), w0
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s16_tied1, svint16_t, svint8_t, int8_t,
+ z0 = svabal_n_s16 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_s16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), w0
+** movprfx z0, z1
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s16_untied, svint16_t, svint8_t, int8_t,
+ z0 = svabal_n_s16 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_s16_tied1:
+** mov (z[0-9]+\.b), #11
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s16_tied1, svint16_t, svint8_t,
+ z0 = svabal_n_s16 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_s16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), #11
+** movprfx z0, z1
+** sabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s16_untied, svint16_t, svint8_t,
+ z0 = svabal_n_s16 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
new file mode 100644
index 00000000000..82390f3adfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s32.c
@@ -0,0 +1,88 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_s32_tied1:
+** sabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_s32_tied1, svint32_t, svint16_t,
+ z0 = svabal_s32 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_s32_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.s, \1\.h, z1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s32_tied2, svint32_t, svint16_t,
+ z0_res = svabal_s32 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_s32_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.s, z1\.h, \1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s32_tied3, svint32_t, svint16_t,
+ z0_res = svabal_s32 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_s32_untied:
+** movprfx z0, z1
+** sabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_s32_untied, svint32_t, svint16_t,
+ z0 = svabal_s32 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_s32_tied1:
+** mov (z[0-9]+\.h), w0
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s32_tied1, svint32_t, svint16_t, int16_t,
+ z0 = svabal_n_s32 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_s32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), w0
+** movprfx z0, z1
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s32_untied, svint32_t, svint16_t, int16_t,
+ z0 = svabal_n_s32 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_s32_tied1:
+** mov (z[0-9]+\.h), #11
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s32_tied1, svint32_t, svint16_t,
+ z0 = svabal_n_s32 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_s32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), #11
+** movprfx z0, z1
+** sabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s32_untied, svint32_t, svint16_t,
+ z0 = svabal_n_s32 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
new file mode 100644
index 00000000000..1b16e665413
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_s64.c
@@ -0,0 +1,88 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_s64_tied1:
+** sabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_s64_tied1, svint64_t, svint32_t,
+ z0 = svabal_s64 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_s64_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.d, \1\.s, z1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s64_tied2, svint64_t, svint32_t,
+ z0_res = svabal_s64 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_s64_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** sabal z0\.d, z1\.s, \1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_s64_tied3, svint64_t, svint32_t,
+ z0_res = svabal_s64 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_s64_untied:
+** movprfx z0, z1
+** sabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_s64_untied, svint64_t, svint32_t,
+ z0 = svabal_s64 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_s64_tied1:
+** mov (z[0-9]+\.s), w0
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s64_tied1, svint64_t, svint32_t, int32_t,
+ z0 = svabal_n_s64 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_s64_untied:
+** mov (z[0-9]+\.s), w0
+** movprfx z0, z1
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_s64_untied, svint64_t, svint32_t, int32_t,
+ z0 = svabal_n_s64 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_s64_tied1:
+** mov (z[0-9]+\.s), #11
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s64_tied1, svint64_t, svint32_t,
+ z0 = svabal_n_s64 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_s64_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.s), #11
+** movprfx z0, z1
+** sabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_s64_untied, svint64_t, svint32_t,
+ z0 = svabal_n_s64 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
new file mode 100644
index 00000000000..6db7dacaad6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u16.c
@@ -0,0 +1,88 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_u16_tied1:
+** uabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_u16_tied1, svuint16_t, svuint8_t,
+ z0 = svabal_u16 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_u16_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.h, \1\.b, z1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u16_tied2, svuint16_t, svuint8_t,
+ z0_res = svabal_u16 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_u16_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.h, z1\.b, \1\.b
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u16_tied3, svuint16_t, svuint8_t,
+ z0_res = svabal_u16 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_u16_untied:
+** movprfx z0, z1
+** uabal z0\.h, z4\.b, z5\.b
+** ret
+*/
+TEST_DUAL_Z (abal_u16_untied, svuint16_t, svuint8_t,
+ z0 = svabal_u16 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_u16_tied1:
+** mov (z[0-9]+\.b), w0
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u16_tied1, svuint16_t, svuint8_t, uint8_t,
+ z0 = svabal_n_u16 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_u16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), w0
+** movprfx z0, z1
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u16_untied, svuint16_t, svuint8_t, uint8_t,
+ z0 = svabal_n_u16 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_u16_tied1:
+** mov (z[0-9]+\.b), #11
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u16_tied1, svuint16_t, svuint8_t,
+ z0 = svabal_n_u16 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_u16_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.b), #11
+** movprfx z0, z1
+** uabal z0\.h, z4\.b, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u16_untied, svuint16_t, svuint8_t,
+ z0 = svabal_n_u16 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
new file mode 100644
index 00000000000..84975987e67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u32.c
@@ -0,0 +1,88 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_u32_tied1:
+** uabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_u32_tied1, svuint32_t, svuint16_t,
+ z0 = svabal_u32 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_u32_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.s, \1\.h, z1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u32_tied2, svuint32_t, svuint16_t,
+ z0_res = svabal_u32 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_u32_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.s, z1\.h, \1\.h
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u32_tied3, svuint32_t, svuint16_t,
+ z0_res = svabal_u32 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_u32_untied:
+** movprfx z0, z1
+** uabal z0\.s, z4\.h, z5\.h
+** ret
+*/
+TEST_DUAL_Z (abal_u32_untied, svuint32_t, svuint16_t,
+ z0 = svabal_u32 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_u32_tied1:
+** mov (z[0-9]+\.h), w0
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u32_tied1, svuint32_t, svuint16_t, uint16_t,
+ z0 = svabal_n_u32 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_u32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), w0
+** movprfx z0, z1
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u32_untied, svuint32_t, svuint16_t, uint16_t,
+ z0 = svabal_n_u32 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_u32_tied1:
+** mov (z[0-9]+\.h), #11
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u32_tied1, svuint32_t, svuint16_t,
+ z0 = svabal_n_u32 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_u32_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.h), #11
+** movprfx z0, z1
+** uabal z0\.s, z4\.h, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u32_untied, svuint32_t, svuint16_t,
+ z0 = svabal_n_u32 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
new file mode 100644
index 00000000000..6189afbba6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/abal_u64.c
@@ -0,0 +1,88 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+#pragma GCC target "+sve2p3"
+#pragma GCC target "+sme2p3"
+
+/*
+** abal_u64_tied1:
+** uabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_u64_tied1, svuint64_t, svuint32_t,
+ z0 = svabal_u64 (z0, z4, z5),
+ z0 = svabal (z0, z4, z5))
+
+/*
+** abal_u64_tied2:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.d, \1\.s, z1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u64_tied2, svuint64_t, svuint32_t,
+ z0_res = svabal_u64 (z4, z0, z1),
+ z0_res = svabal (z4, z0, z1))
+
+/*
+** abal_u64_tied3:
+** mov (z[0-9]+)\.d, z0\.d
+** movprfx z0, z4
+** uabal z0\.d, z1\.s, \1\.s
+** ret
+*/
+TEST_DUAL_Z_REV (abal_u64_tied3, svuint64_t, svuint32_t,
+ z0_res = svabal_u64 (z4, z1, z0),
+ z0_res = svabal (z4, z1, z0))
+
+/*
+** abal_u64_untied:
+** movprfx z0, z1
+** uabal z0\.d, z4\.s, z5\.s
+** ret
+*/
+TEST_DUAL_Z (abal_u64_untied, svuint64_t, svuint32_t,
+ z0 = svabal_u64 (z1, z4, z5),
+ z0 = svabal (z1, z4, z5))
+
+/*
+** abal_w0_u64_tied1:
+** mov (z[0-9]+\.s), w0
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u64_tied1, svuint64_t, svuint32_t, uint32_t,
+ z0 = svabal_n_u64 (z0, z4, x0),
+ z0 = svabal (z0, z4, x0))
+
+/*
+** abal_w0_u64_untied:
+** mov (z[0-9]+\.s), w0
+** movprfx z0, z1
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_ZX (abal_w0_u64_untied, svuint64_t, svuint32_t, uint32_t,
+ z0 = svabal_n_u64 (z1, z4, x0),
+ z0 = svabal (z1, z4, x0))
+
+/*
+** abal_11_u64_tied1:
+** mov (z[0-9]+\.s), #11
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u64_tied1, svuint64_t, svuint32_t,
+ z0 = svabal_n_u64 (z0, z4, 11),
+ z0 = svabal (z0, z4, 11))
+
+/*
+** abal_11_u64_untied:: { xfail *-*-*}
+** mov (z[0-9]+\.s), #11
+** movprfx z0, z1
+** uabal z0\.d, z4\.s, \1
+** ret
+*/
+TEST_DUAL_Z (abal_11_u64_untied, svuint64_t, svuint32_t,
+ z0 = svabal_n_u64 (z1, z4, 11),
+ z0 = svabal (z1, z4, 11))
--
2.43.0
