From: Richard Ball <[email protected]>
---
gcc/config/aarch64/aarch64.h | 8 ++++++++
gcc/doc/invoke.texi | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 184c732c3ab..fbdae6ec183 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -318,6 +318,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
/* SVE2p2 instructions, enabled through +sve2p2. */
#define TARGET_SVE2p2 AARCH64_HAVE_ISA (SVE2p2)
+#define TARGET_SVE2p3 AARCH64_HAVE_ISA (SVE2p3)
+
/* SME instructions, enabled through +sme. Note that this does not
imply anything about the state of PSTATE.SM; instructions that require
SME and streaming mode should use TARGET_STREAMING instead. */
@@ -351,11 +353,15 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
ATTRIBUTE_UNUSED
/* SME2p2 instructions, enabled through +sme2p2. */
#define TARGET_SME2p2 AARCH64_HAVE_ISA (SME2p2)
+#define TARGET_SME2p3 AARCH64_HAVE_ISA (SME2p3)
+
/* Same with streaming mode enabled. */
#define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2)
#define TARGET_STREAMING_SME2p1 (TARGET_STREAMING && AARCH64_HAVE_ISA (SME2p1))
+#define TARGET_STREAMING_SME2p3 (TARGET_STREAMING && AARCH64_HAVE_ISA (SME2p3))
+
#define TARGET_STREAMING_SME2p2 (TARGET_STREAMING && AARCH64_HAVE_ISA (SME2p2))
#define TARGET_STREAMING_SME_TMOP \
@@ -537,6 +543,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
functions, since streaming mode itself implies SME. */
#define TARGET_SVE2p1_OR_SME (TARGET_SVE2p1 || TARGET_STREAMING)
+#define TARGET_SVE2p3_OR_SME2p3 (TARGET_SVE2p3 || TARGET_SME2p3)
+
#define TARGET_SVE2p1_OR_SME2 \
((TARGET_SVE2p1 || TARGET_STREAMING) \
&& (TARGET_SME2 || TARGET_NON_STREAMING))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a622c783216..d6cf1831ceb 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21936,6 +21936,8 @@ Enable SVE2 sha3 instructions. This also enables SVE2
instructions.
Enable SVE2.1 instructions. This also enables SVE2 instructions.
@item sve2p2
Enable SVE2.2 instructions. This also enables SVE2 and SVE2.1 instructions.
+@item sve2p3
+Enable SVE2.3 instructions. This also enables SVE2 instructions.
@item tme
Enable the Transactional Memory Extension.
@item i8mm
@@ -22004,6 +22006,8 @@ instructions.
@item sme2p2
Enable the Scalable Matrix Extension version 2.2. This also enables SME2
and SME2.1 instructions.
+@item sme2p3
+Enable the Scalable Matrix Extension version 2.3. This also enables SME2
@item fcma
Enable the complex number SIMD extensions.
@item jscvt
--
2.43.0
