From: Karl Meakin <[email protected]>
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (SME_F8F16): New opt
extension.
(SME_F8F32): Likewise.
(SME_MOP4): Likewise.
* doc/invoke.texi: Document new extension flags.
* config/aarch64/aarch64.h (TARGET_SME_F8F16): New target macro.
(TARGET_SME_F8F32): Likewise.
(TARGET_SME_MOP4): Likewise.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
`__ARM_FEATURE_SME_F8F16`, `__ARM_FEATURE_SME_F8F32` and
`__ARM_FEATURE_SME_MOP4` macros when the relevent extension is enabled.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Test that
`__ARM_FEATURE_SME_F8F16`, `__ARM_FEATURE_SME_F8F32`
and `__ARM_FEATURE_SME_MOP4` macros are defined when the relevelant
extension is enabled.
---
gcc/config/aarch64/aarch64-c.cc | 2 ++
gcc/config/aarch64/aarch64.h | 2 ++
gcc/doc/invoke.texi | 3 +++
gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index e6a9b31cd4f..21ced615c10 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -312,6 +312,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
"__ARM_FEATURE_SME_F16F16", pfile);
aarch64_def_or_undef (TARGET_SME_F64F64, "__ARM_FEATURE_SME_F64F64", pfile);
aarch64_def_or_undef (TARGET_SME2, "__ARM_FEATURE_SME2", pfile);
+ aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_MOP4), "__ARM_FEATURE_SME_MOP4",
+ pfile);
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME2p1),
"__ARM_FEATURE_SME2p1", pfile);
aarch64_def_or_undef (TARGET_SME2p2, "__ARM_FEATURE_SME2p2", pfile);
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index f425bb3493a..3a62607cbf9 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -502,6 +502,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
elements are enabled through +sme-lutv2. */
#define TARGET_SME_LUTv2 AARCH64_HAVE_ISA (SME_LUTv2)
+#define TARGET_SME_MOP4 (AARCH64_HAVE_ISA (SME_MOP4) && TARGET_STREAMING)
+
/* Prefer different predicate registers for the output of a predicated
operation over re-using an existing input predicate. */
#define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 339d1d2c97a..a622c783216 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21995,6 +21995,9 @@ and SVE_B16B16 instructions.
@item sme-f16f16
Enable the FEAT_SME_F16F16 extension to SME. This also enables SME2
instructions.
+@item sme-mop4
+Enable the FEAT_SME_MOP4 extension to SME. This also enables SME2
+instructions.
@item sme2p1
Enable the Scalable Matrix Extension version 2.1. This also enables SME2
instructions.
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
index 0f750aba170..cb009ec2752 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
@@ -232,6 +232,11 @@
#error Foo
#endif
+#pragma GCC target "+nothing+sve2+sme-mop4"
+#ifndef __ARM_FEATURE_SME_MOP4
+#error "__ARM_FEATURE_SME_MOP4 not defined"
+#endif
+
#pragma GCC target "branch-protection=standard"
#ifndef __ARM_FEATURE_BTI_DEFAULT
#error Foo
--
2.43.0
