From: Richard Ball <[email protected]>
---
.../aarch64/aarch64-sve-builtins-sve2.cc | 48 ++++++++++++
.../aarch64/aarch64-sve-builtins-sve2.def | 3 +
.../aarch64/aarch64-sve-builtins-sve2.h | 3 +
gcc/config/aarch64/aarch64-sve-builtins.cc | 18 +++++
gcc/config/aarch64/aarch64-sve2.md | 74 +++++++++++++++++++
gcc/config/aarch64/iterators.md | 16 +++-
.../aarch64/sme2/acle-asm/cvtb_f16_s8.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtb_f16_u8.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtb_f32_s16.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtb_f32_u16.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtb_f64_s32.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtb_f64_u32.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtt_f16_s8.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtt_f16_u8.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtt_f32_s16.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtt_f32_u16.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtt_f64_s32.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtt_f64_u32.c | 22 ++++++
.../aarch64/sme2/acle-asm/cvtzn_s16_f32_x2.c | 51 +++++++++++++
.../aarch64/sme2/acle-asm/cvtzn_s32_f64_x2.c | 51 +++++++++++++
.../aarch64/sme2/acle-asm/cvtzn_s8_f16_x2.c | 51 +++++++++++++
.../aarch64/sme2/acle-asm/cvtzn_u16_f32_x2.c | 51 +++++++++++++
.../aarch64/sme2/acle-asm/cvtzn_u32_f64_x2.c | 51 +++++++++++++
.../aarch64/sme2/acle-asm/cvtzn_u8_f16_x2.c | 51 +++++++++++++
24 files changed, 731 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s16_f32_x2.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s32_f64_x2.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s8_f16_x2.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u16_f32_x2.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u32_f64_x2.c
create mode 100644
gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u8_f16_x2.c
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
index ceb6be97f67..56f64fa0e37 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
@@ -252,6 +252,51 @@ public:
}
};
+class svcvtzn_impl : public function_base
+{
+public:
+ rtx
+ expand (function_expander &e) const override
+ {
+ insn_code icode;
+ if (e.type_suffix (0).unsigned_p)
+ icode = code_for_aarch64_sve2_fcvtzun (e.result_mode ());
+ else
+ icode = code_for_aarch64_sve2_fcvtzsn (e.result_mode ());
+ return e.use_exact_insn (icode);
+ }
+};
+
+class svcvtt_impl : public function_base
+{
+public:
+ rtx
+ expand (function_expander &e) const override
+ {
+ insn_code icode;
+ if (e.type_suffix (1).unsigned_p)
+ icode = code_for_aarch64_sve2_ucvtflt (e.result_mode ());
+ else
+ icode = code_for_aarch64_sve2_scvtflt (e.result_mode ());
+ return e.use_exact_insn (icode);
+ }
+};
+
+class svcvtb_impl : public function_base
+{
+public:
+ rtx
+ expand (function_expander &e) const override
+ {
+ insn_code icode;
+ if (e.type_suffix (1).unsigned_p)
+ icode = code_for_aarch64_sve2_ucvtfb (e.result_mode ());
+ else
+ icode = code_for_aarch64_sve2_scvtfb (e.result_mode ());
+ return e.use_exact_insn (icode);
+ }
+};
+
class svdup_laneq_impl : public function_base
{
public:
@@ -1073,9 +1118,12 @@ FUNCTION (svcvtlt1, svcvt_fp8_impl, (UNSPEC_F1CVTLT))
FUNCTION (svcvtlt2, svcvt_fp8_impl, (UNSPEC_F2CVTLT))
FUNCTION (svcvtlt, unspec_based_function, (-1, -1, UNSPEC_COND_FCVTLT))
FUNCTION (svcvtn, svcvtn_impl,)
+FUNCTION (svcvtzn, svcvtzn_impl,)
FUNCTION (svcvtnb, fixed_insn_function,
(CODE_FOR_aarch64_sve2_fp8_cvtnbvnx16qi))
FUNCTION (svcvtx, unspec_based_function, (-1, -1, UNSPEC_COND_FCVTX))
FUNCTION (svcvtxnt, NARROWING_TOP_CONVERT1 (aarch64_sve2_cvtxnt),)
+FUNCTION (svcvtt, svcvtt_impl,)
+FUNCTION (svcvtb, svcvtb_impl,)
FUNCTION (svdup_laneq, svdup_laneq_impl,)
FUNCTION (sveor3, CODE_FOR_MODE0 (aarch64_sve2_eor3),)
FUNCTION (sveorbt, unspec_based_function, (UNSPEC_EORBT, UNSPEC_EORBT, -1))
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
index 93d313336f0..b77ccd06205 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
@@ -322,6 +322,9 @@ DEF_SVE_FUNCTION_GS (svqrshrn, shift_right_imm_narrowxn,
qrshr_x2_sve2p3, x2, no
DEF_SVE_FUNCTION_GS (svqrshrun, shift_right_imm_narrowxn, qrshrun_x2_sve2p3,
x2, none)
DEF_SVE_FUNCTION_GS (svqshrn, shift_right_imm_narrowxn, qshr_x2_sve2p3, x2,
none)
DEF_SVE_FUNCTION_GS (svqshrun, shift_right_imm_narrowxn, qshru_x2_sve2p3, x2,
none)
+DEF_SVE_FUNCTION_GS (svcvtzn, unary_convertxn, cvtzn, x2, none)
+DEF_SVE_FUNCTION (svcvtt, unary_convert, cvttb, none)
+DEF_SVE_FUNCTION (svcvtb, unary_convert, cvttb, none)
#undef REQUIRED_EXTENSIONS
#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2)
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
index 64b44dce7a8..d2b193776c7 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
@@ -70,6 +70,9 @@ namespace aarch64_sve
extern const function_base *const svcvtlt1;
extern const function_base *const svcvtlt2;
extern const function_base *const svcvtn;
+ extern const function_base *const svcvtzn;
+ extern const function_base *const svcvtt;
+ extern const function_base *const svcvtb;
extern const function_base *const svcvtnb;
extern const function_base *const svcvtnt;
extern const function_base *const svcvtx;
diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc
b/gcc/config/aarch64/aarch64-sve-builtins.cc
index b4a2da1bfb9..34ad120ab4e 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
@@ -514,6 +514,22 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {
#define TYPES_cvtnx_mf8(S, D, T) \
D (mf8, f32)
+#define TYPES_cvtzn(S, D, T) \
+ D (s8, f16), \
+ D (u8, f16), \
+ D (s16, f32), \
+ D (u16, f32), \
+ D (s32, f64), \
+ D (u32, f64)
+
+#define TYPES_cvttb(S, D, T) \
+ D (f16, s8), \
+ D (f16, u8), \
+ D (f32, s16), \
+ D (f32, u16), \
+ D (f64, s32), \
+ D (f64, u32)
+
/* { _s32 _s64 } x { _b8 _b16 _b32 _b64 }
{ _u32 _u64 }. */
#define TYPES_inc_dec_n1(D, A) \
@@ -956,6 +972,8 @@ DEF_SVE_TYPES_ARRAY (cvt_narrow);
DEF_SVE_TYPES_ARRAY (cvt_s_s);
DEF_SVE_TYPES_ARRAY (cvtn_mf8);
DEF_SVE_TYPES_ARRAY (cvtnx_mf8);
+DEF_SVE_TYPES_ARRAY (cvtzn);
+DEF_SVE_TYPES_ARRAY (cvttb);
DEF_SVE_TYPES_ARRAY (inc_dec_n);
DEF_SVE_TYPES_ARRAY (qcvt_x2);
DEF_SVE_TYPES_ARRAY (qcvt_x4);
diff --git a/gcc/config/aarch64/aarch64-sve2.md
b/gcc/config/aarch64/aarch64-sve2.md
index 817d9ba6ea7..b9d527d9813 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -105,6 +105,7 @@
;; == Conversions
;; ---- [FP<-FP] Widening conversions
;; ---- [FP<-FP] Narrowing conversions
+;; ---- [FP<-INT] Widening conversions
;; ---- [FP<-FP] Multi-vector widening conversions
;; ---- [FP<-FP] Multi-vector narrowing conversions
;; ---- [FP<-INT] Multi-vector conversions
@@ -3796,6 +3797,57 @@ (define_insn "@aarch64_sve2_cvtxnt<mode>"
[(set_attr "sve_type" "sve_fp_cvt")]
)
+;; -------------------------------------------------------------------------
+;; ---- [FP<-INT] Widening conversions
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - SCVTF (SME_2p3)
+;; - SCVTFLT (SME_2p3)
+;; - UCVTF (SME_2p3)
+;; - UCVTFLT (SME_2p3)
+;; -------------------------------------------------------------------------
+
+(define_insn "@aarch64_sve2_scvtfb<mode>"
+ [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
+ (unspec:SVE_FULL_F
+ [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
+ UNSPEC_SCVTFB))]
+ "TARGET_SVE2p3_OR_SME2p3"
+ "scvtf\t%0.<Vetype>, %1.<Ventype>"
+ [(set_attr "sve_type" "sve_fp_cvt")]
+)
+
+(define_insn "@aarch64_sve2_scvtflt<mode>"
+ [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
+ (unspec:SVE_FULL_F
+ [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
+ UNSPEC_SCVTFLT))]
+ "TARGET_SVE2p3_OR_SME2p3"
+ "scvtflt\t%0.<Vetype>, %1.<Ventype>"
+ [(set_attr "sve_type" "sve_fp_cvt")]
+)
+
+(define_insn "@aarch64_sve2_ucvtfb<mode>"
+ [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
+ (unspec:SVE_FULL_F
+ [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
+ UNSPEC_UCVTFB))]
+ "TARGET_SVE2p3_OR_SME2p3"
+ "ucvtf\t%0.<Vetype>, %1.<Ventype>"
+ [(set_attr "sve_type" "sve_fp_cvt")]
+)
+
+(define_insn "@aarch64_sve2_ucvtflt<mode>"
+ [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w")
+ (unspec:SVE_FULL_F
+ [(match_operand:<CVTTB_SRC> 1 "register_operand" "w")]
+ UNSPEC_UCVTFLT))]
+ "TARGET_SVE2p3_OR_SME2p3"
+ "ucvtflt\t%0.<Vetype>, %1.<Ventype>"
+ [(set_attr "sve_type" "sve_fp_cvt")]
+)
+
+
;; -------------------------------------------------------------------------
;; ---- [FP<-FP] Multi-vector widening conversions
@@ -3932,6 +3984,8 @@ (define_insn "<optab><v_int_equiv><mode>2"
;; Includes the multi-register forms of:
;; - FCVTZS (SME2)
;; - FCVTZU (SME2)
+;; - FCVTZSN (SME2p3)
+;; - FCVTZUN (SME2p3)
;; -------------------------------------------------------------------------
(define_insn "<optab><mode><v_int_equiv>2"
@@ -3943,6 +3997,26 @@ (define_insn "<optab><mode><v_int_equiv>2"
[(set_attr "sve_type" "sve_fp_cvt")]
)
+(define_insn "@aarch64_sve2_fcvtzsn<mode>"
+ [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
+ (unspec:SVE_FULL_BHSI
+ [(match_operand:<FCVTZN_SRC> 1 "aligned_register_operand" "Uw2")]
+ UNSPEC_FCVTZSN))]
+ "TARGET_SVE2p3_OR_SME2p3"
+ "fcvtzsn\t%0.<Vetype>, %1"
+ [(set_attr "sve_type" "sve_fp_cvt")]
+)
+
+(define_insn "@aarch64_sve2_fcvtzun<mode>"
+ [(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
+ (unspec:SVE_FULL_BHSI
+ [(match_operand:<FCVTZN_SRC> 1 "aligned_register_operand" "Uw2")]
+ UNSPEC_FCVTZUN))]
+ "TARGET_SVE2p3_OR_SME2p3"
+ "fcvtzun\t%0.<Vetype>, %1"
+ [(set_attr "sve_type" "sve_fp_cvt")]
+)
+
;; =========================================================================
;; == Other arithmetic
;; =========================================================================
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 5ef53d9fdbd..108c2f886d5 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -1153,6 +1153,12 @@ (define_c_enum "unspec"
UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md.
UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md.
UNSPEC_COND_FCVTXNT ; Used in aarch64-sve2.md.
+ UNSPEC_FCVTZSN ; Used in aarch64-sve2.md.
+ UNSPEC_FCVTZUN ; Used in aarch64-sve2.md.
+ UNSPEC_SCVTFB ; Used in aarch64-sve2.md.
+ UNSPEC_SCVTFLT ; Used in aarch64-sve2.md.
+ UNSPEC_UCVTFB ; Used in aarch64-sve2.md.
+ UNSPEC_UCVTFLT ; Used in aarch64-sve2.md.
UNSPEC_COND_FLOGB ; Used in aarch64-sve2.md.
UNSPEC_DOT_FP8 ; Used in aarch64-sve2.md.
UNSPEC_DOT_LANE_FP8 ; Used in aarch64-sve2.md.
@@ -2327,7 +2333,7 @@ (define_mode_attr Vwhalf [(V8QI "4h") (V4HI "2s")
(V8HI "4s") (V4SI "2d")])
;; SVE vector after narrowing.
-(define_mode_attr Ventype [(VNx8HI "b")
+(define_mode_attr Ventype [(VNx8HI "b") (VNx8HF "b")
(VNx16HI "b")
(VNx4SI "h") (VNx4SF "h")
(VNx2DI "s") (VNx2DF "s")
@@ -2956,6 +2962,14 @@ (define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>")
(V4SF "<Vetype>[%4]")
(V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
])
+(define_mode_attr FCVTZN_SRC [(VNx16QI "VNx16HF")
+ (VNx8HI "VNx8SF")
+ (VNx4SI "VNx4DF")])
+
+(define_mode_attr CVTTB_SRC [(VNx8HF "VNx16QI")
+ (VNx4SF "VNx8HI")
+ (VNx2DF "VNx4SI")])
+
(define_mode_attr za16_offset_range [(VNx16QI "0_to_14_step_2")
(VNx32QI "0_to_6_step_2")
(VNx64QI "0_to_6_step_2")])
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
new file mode 100644
index 00000000000..2d0a9bf434f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_s8.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtb_untied:
+** scvtf z0\.h, z4\.b
+** ret
+*/
+TEST_DUAL_Z (cvtb_untied, svfloat16_t, svint8_t,
+ z0 = svcvtb_f16_s8 (z4),
+ z0 = svcvtb_f16 (z4))
+
+/*
+** cvtb_tied:
+** scvtf z0\.h, z0\.b
+** ret
+*/
+TEST_DUAL_Z_REV (cvtb_tied, svfloat16_t, svint8_t,
+ z0_res = svcvtb_f16_s8 (z0),
+ z0_res = svcvtb_f16 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
new file mode 100644
index 00000000000..670ab5153a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f16_u8.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtb_untied:
+** ucvtf z0\.h, z4\.b
+** ret
+*/
+TEST_DUAL_Z (cvtb_untied, svfloat16_t, svuint8_t,
+ z0 = svcvtb_f16_u8 (z4),
+ z0 = svcvtb_f16 (z4))
+
+/*
+** cvtb_tied:
+** ucvtf z0\.h, z0\.b
+** ret
+*/
+TEST_DUAL_Z_REV (cvtb_tied, svfloat16_t, svuint8_t,
+ z0_res = svcvtb_f16_u8 (z0),
+ z0_res = svcvtb_f16 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
new file mode 100644
index 00000000000..b51880b1364
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_s16.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtb_untied:
+** scvtf z0\.s, z4\.h
+** ret
+*/
+TEST_DUAL_Z (cvtb_untied, svfloat32_t, svint16_t,
+ z0 = svcvtb_f32_s16 (z4),
+ z0 = svcvtb_f32 (z4))
+
+/*
+** cvtb_tied:
+** scvtf z0\.s, z0\.h
+** ret
+*/
+TEST_DUAL_Z_REV (cvtb_tied, svfloat32_t, svint16_t,
+ z0_res = svcvtb_f32_s16 (z0),
+ z0_res = svcvtb_f32 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
new file mode 100644
index 00000000000..5a16e4a6246
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f32_u16.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtb_untied:
+** ucvtf z0\.s, z4\.h
+** ret
+*/
+TEST_DUAL_Z (cvtb_untied, svfloat32_t, svuint16_t,
+ z0 = svcvtb_f32_u16 (z4),
+ z0 = svcvtb_f32 (z4))
+
+/*
+** cvtb_tied:
+** ucvtf z0\.s, z0\.h
+** ret
+*/
+TEST_DUAL_Z_REV (cvtb_tied, svfloat32_t, svuint16_t,
+ z0_res = svcvtb_f32_u16 (z0),
+ z0_res = svcvtb_f32 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
new file mode 100644
index 00000000000..6aafc5792ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_s32.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtb_untied:
+** scvtf z0\.d, z4\.s
+** ret
+*/
+TEST_DUAL_Z (cvtb_untied, svfloat64_t, svint32_t,
+ z0 = svcvtb_f64_s32 (z4),
+ z0 = svcvtb_f64 (z4))
+
+/*
+** cvtb_tied:
+** scvtf z0\.d, z0\.s
+** ret
+*/
+TEST_DUAL_Z_REV (cvtb_tied, svfloat64_t, svint32_t,
+ z0_res = svcvtb_f64_s32 (z0),
+ z0_res = svcvtb_f64 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
new file mode 100644
index 00000000000..7ee9a2157ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtb_f64_u32.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtb_untied:
+** ucvtf z0\.d, z4\.s
+** ret
+*/
+TEST_DUAL_Z (cvtb_untied, svfloat64_t, svuint32_t,
+ z0 = svcvtb_f64_u32 (z4),
+ z0 = svcvtb_f64 (z4))
+
+/*
+** cvtb_tied:
+** ucvtf z0\.d, z0\.s
+** ret
+*/
+TEST_DUAL_Z_REV (cvtb_tied, svfloat64_t, svuint32_t,
+ z0_res = svcvtb_f64_u32 (z0),
+ z0_res = svcvtb_f64 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
new file mode 100644
index 00000000000..4352e484bf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_s8.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtt_untied:
+** scvtflt z0\.h, z4\.b
+** ret
+*/
+TEST_DUAL_Z (cvtt_untied, svfloat16_t, svint8_t,
+ z0 = svcvtt_f16_s8 (z4),
+ z0 = svcvtt_f16 (z4))
+
+/*
+** cvtt_tied:
+** scvtflt z0\.h, z0\.b
+** ret
+*/
+TEST_DUAL_Z_REV (cvtt_tied, svfloat16_t, svint8_t,
+ z0_res = svcvtt_f16_s8 (z0),
+ z0_res = svcvtt_f16 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
new file mode 100644
index 00000000000..546a8c432d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f16_u8.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtt_untied:
+** ucvtflt z0\.h, z4\.b
+** ret
+*/
+TEST_DUAL_Z (cvtt_untied, svfloat16_t, svuint8_t,
+ z0 = svcvtt_f16_u8 (z4),
+ z0 = svcvtt_f16 (z4))
+
+/*
+** cvtt_tied:
+** ucvtflt z0\.h, z0\.b
+** ret
+*/
+TEST_DUAL_Z_REV (cvtt_tied, svfloat16_t, svuint8_t,
+ z0_res = svcvtt_f16_u8 (z0),
+ z0_res = svcvtt_f16 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
new file mode 100644
index 00000000000..c1b856af0fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_s16.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtt_untied:
+** scvtflt z0\.s, z4\.h
+** ret
+*/
+TEST_DUAL_Z (cvtt_untied, svfloat32_t, svint16_t,
+ z0 = svcvtt_f32_s16 (z4),
+ z0 = svcvtt_f32 (z4))
+
+/*
+** cvtt_tied:
+** scvtflt z0\.s, z0\.h
+** ret
+*/
+TEST_DUAL_Z_REV (cvtt_tied, svfloat32_t, svint16_t,
+ z0_res = svcvtt_f32_s16 (z0),
+ z0_res = svcvtt_f32 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
new file mode 100644
index 00000000000..7701d97eb4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f32_u16.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtt_untied:
+** ucvtflt z0\.s, z4\.h
+** ret
+*/
+TEST_DUAL_Z (cvtt_untied, svfloat32_t, svuint16_t,
+ z0 = svcvtt_f32_u16 (z4),
+ z0 = svcvtt_f32 (z4))
+
+/*
+** cvtt_tied:
+** ucvtflt z0\.s, z0\.h
+** ret
+*/
+TEST_DUAL_Z_REV (cvtt_tied, svfloat32_t, svuint16_t,
+ z0_res = svcvtt_f32_u16 (z0),
+ z0_res = svcvtt_f32 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
new file mode 100644
index 00000000000..e18734d0c8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_s32.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtt_untied:
+** scvtflt z0\.d, z4\.s
+** ret
+*/
+TEST_DUAL_Z (cvtt_untied, svfloat64_t, svint32_t,
+ z0 = svcvtt_f64_s32 (z4),
+ z0 = svcvtt_f64 (z4))
+
+/*
+** cvtt_tied:
+** scvtflt z0\.d, z0\.s
+** ret
+*/
+TEST_DUAL_Z_REV (cvtt_tied, svfloat64_t, svint32_t,
+ z0_res = svcvtt_f64_s32 (z0),
+ z0_res = svcvtt_f64 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
new file mode 100644
index 00000000000..b0078952ed5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtt_f64_u32.c
@@ -0,0 +1,22 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtt_untied:
+** ucvtflt z0\.d, z4\.s
+** ret
+*/
+TEST_DUAL_Z (cvtt_untied, svfloat64_t, svuint32_t,
+ z0 = svcvtt_f64_u32 (z4),
+ z0 = svcvtt_f64 (z4))
+
+/*
+** cvtt_tied:
+** ucvtflt z0\.d, z0\.s
+** ret
+*/
+TEST_DUAL_Z_REV (cvtt_tied, svfloat64_t, svuint32_t,
+ z0_res = svcvtt_f64_u32 (z0),
+ z0_res = svcvtt_f64 (z0))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s16_f32_x2.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s16_f32_x2.c
new file mode 100644
index 00000000000..c17e7492ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s16_f32_x2.c
@@ -0,0 +1,51 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtzn_z0_z0:
+** fcvtzsn z0\.h, {z0\.s - z1\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z0, svfloat32x2_t, svint16_t,
+ z0_res = svcvtzn_s16_f32_x2 (z0),
+ z0_res = svcvtzn_s16 (z0))
+
+/*
+** cvtzn_z0_z6:
+** fcvtzsn z0\.h, {z6\.s - z7\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z6, svfloat32x2_t, svint16_t,
+ z0_res = svcvtzn_s16_f32_x2 (z6),
+ z0_res = svcvtzn_s16 (z6))
+
+/*
+** cvtzn_z0_z29:
+** mov [^\n]+
+** mov [^\n]+
+** fcvtzsn z0\.h, [^\n]+
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z29, svfloat32x2_t, svint16_t,
+ z0_res = svcvtzn_s16_f32_x2 (z29),
+ z0_res = svcvtzn_s16 (z29))
+
+/*
+** cvtzn_z5_z0:
+** fcvtzsn z5\.h, {z0\.s - z1\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z5_z0, svfloat32x2_t, svint16_t,
+ z5 = svcvtzn_s16_f32_x2 (z0),
+ z5 = svcvtzn_s16 (z0))
+
+/*
+** cvtzn_z22_z16:
+** fcvtzsn z22\.h, {z16\.s - z17\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z22_z16, svfloat32x2_t, svint16_t,
+ z22 = svcvtzn_s16_f32_x2 (z16),
+ z22 = svcvtzn_s16 (z16))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s32_f64_x2.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s32_f64_x2.c
new file mode 100644
index 00000000000..77dbdadb85d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s32_f64_x2.c
@@ -0,0 +1,51 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtzn_z0_z0:
+** fcvtzsn z0\.s, {z0\.d - z1\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z0, svfloat64x2_t, svint32_t,
+ z0_res = svcvtzn_s32_f64_x2 (z0),
+ z0_res = svcvtzn_s32 (z0))
+
+/*
+** cvtzn_z0_z6:
+** fcvtzsn z0\.s, {z6\.d - z7\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z6, svfloat64x2_t, svint32_t,
+ z0_res = svcvtzn_s32_f64_x2 (z6),
+ z0_res = svcvtzn_s32 (z6))
+
+/*
+** cvtzn_z0_z29:
+** mov [^\n]+
+** mov [^\n]+
+** fcvtzsn z0\.s, [^\n]+
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z29, svfloat64x2_t, svint32_t,
+ z0_res = svcvtzn_s32_f64_x2 (z29),
+ z0_res = svcvtzn_s32 (z29))
+
+/*
+** cvtzn_z5_z0:
+** fcvtzsn z5\.s, {z0\.d - z1\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z5_z0, svfloat64x2_t, svint32_t,
+ z5 = svcvtzn_s32_f64_x2 (z0),
+ z5 = svcvtzn_s32 (z0))
+
+/*
+** cvtzn_z22_z16:
+** fcvtzsn z22\.s, {z16\.d - z17\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z22_z16, svfloat64x2_t, svint32_t,
+ z22 = svcvtzn_s32_f64_x2 (z16),
+ z22 = svcvtzn_s32 (z16))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s8_f16_x2.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s8_f16_x2.c
new file mode 100644
index 00000000000..1d80651576b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_s8_f16_x2.c
@@ -0,0 +1,51 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtzn_z0_z0:
+** fcvtzsn z0\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z0, svfloat16x2_t, svint8_t,
+ z0_res = svcvtzn_s8_f16_x2 (z0),
+ z0_res = svcvtzn_s8 (z0))
+
+/*
+** cvtzn_z0_z6:
+** fcvtzsn z0\.b, {z6\.h - z7\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z6, svfloat16x2_t, svint8_t,
+ z0_res = svcvtzn_s8_f16_x2 (z6),
+ z0_res = svcvtzn_s8 (z6))
+
+/*
+** cvtzn_z0_z29:
+** mov [^\n]+
+** mov [^\n]+
+** fcvtzsn z0\.b, [^\n]+
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z29, svfloat16x2_t, svint8_t,
+ z0_res = svcvtzn_s8_f16_x2 (z29),
+ z0_res = svcvtzn_s8 (z29))
+
+/*
+** cvtzn_z5_z0:
+** fcvtzsn z5\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z5_z0, svfloat16x2_t, svint8_t,
+ z5 = svcvtzn_s8_f16_x2 (z0),
+ z5 = svcvtzn_s8 (z0))
+
+/*
+** cvtzn_z22_z16:
+** fcvtzsn z22\.b, {z16\.h - z17\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z22_z16, svfloat16x2_t, svint8_t,
+ z22 = svcvtzn_s8_f16_x2 (z16),
+ z22 = svcvtzn_s8 (z16))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u16_f32_x2.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u16_f32_x2.c
new file mode 100644
index 00000000000..756bb2899e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u16_f32_x2.c
@@ -0,0 +1,51 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtzn_z0_z0:
+** fcvtzun z0\.h, {z0\.s - z1\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z0, svfloat32x2_t, svuint16_t,
+ z0_res = svcvtzn_u16_f32_x2 (z0),
+ z0_res = svcvtzn_u16 (z0))
+
+/*
+** cvtzn_z0_z6:
+** fcvtzun z0\.h, {z6\.s - z7\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z6, svfloat32x2_t, svuint16_t,
+ z0_res = svcvtzn_u16_f32_x2 (z6),
+ z0_res = svcvtzn_u16 (z6))
+
+/*
+** cvtzn_z0_z29:
+** mov [^\n]+
+** mov [^\n]+
+** fcvtzun z0\.h, [^\n]+
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z29, svfloat32x2_t, svuint16_t,
+ z0_res = svcvtzn_u16_f32_x2 (z29),
+ z0_res = svcvtzn_u16 (z29))
+
+/*
+** cvtzn_z5_z0:
+** fcvtzun z5\.h, {z0\.s - z1\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z5_z0, svfloat32x2_t, svuint16_t,
+ z5 = svcvtzn_u16_f32_x2 (z0),
+ z5 = svcvtzn_u16 (z0))
+
+/*
+** cvtzn_z22_z16:
+** fcvtzun z22\.h, {z16\.s - z17\.s}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z22_z16, svfloat32x2_t, svuint16_t,
+ z22 = svcvtzn_u16_f32_x2 (z16),
+ z22 = svcvtzn_u16 (z16))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u32_f64_x2.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u32_f64_x2.c
new file mode 100644
index 00000000000..ee932f3a07e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u32_f64_x2.c
@@ -0,0 +1,51 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtzn_z0_z0:
+** fcvtzun z0\.s, {z0\.d - z1\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z0, svfloat64x2_t, svuint32_t,
+ z0_res = svcvtzn_u32_f64_x2 (z0),
+ z0_res = svcvtzn_u32 (z0))
+
+/*
+** cvtzn_z0_z6:
+** fcvtzun z0\.s, {z6\.d - z7\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z6, svfloat64x2_t, svuint32_t,
+ z0_res = svcvtzn_u32_f64_x2 (z6),
+ z0_res = svcvtzn_u32 (z6))
+
+/*
+** cvtzn_z0_z29:
+** mov [^\n]+
+** mov [^\n]+
+** fcvtzun z0\.s, [^\n]+
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z29, svfloat64x2_t, svuint32_t,
+ z0_res = svcvtzn_u32_f64_x2 (z29),
+ z0_res = svcvtzn_u32 (z29))
+
+/*
+** cvtzn_z5_z0:
+** fcvtzun z5\.s, {z0\.d - z1\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z5_z0, svfloat64x2_t, svuint32_t,
+ z5 = svcvtzn_u32_f64_x2 (z0),
+ z5 = svcvtzn_u32 (z0))
+
+/*
+** cvtzn_z22_z16:
+** fcvtzun z22\.s, {z16\.d - z17\.d}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z22_z16, svfloat64x2_t, svuint32_t,
+ z22 = svcvtzn_u32_f64_x2 (z16),
+ z22 = svcvtzn_u32 (z16))
diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u8_f16_x2.c
b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u8_f16_x2.c
new file mode 100644
index 00000000000..700e54b0d1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtzn_u8_f16_x2.c
@@ -0,0 +1,51 @@
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+#pragma GCC target "+sme2p3"
+
+/*
+** cvtzn_z0_z0:
+** fcvtzun z0\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z0, svfloat16x2_t, svuint8_t,
+ z0_res = svcvtzn_u8_f16_x2 (z0),
+ z0_res = svcvtzn_u8 (z0))
+
+/*
+** cvtzn_z0_z6:
+** fcvtzun z0\.b, {z6\.h - z7\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z6, svfloat16x2_t, svuint8_t,
+ z0_res = svcvtzn_u8_f16_x2 (z6),
+ z0_res = svcvtzn_u8 (z6))
+
+/*
+** cvtzn_z0_z29:
+** mov [^\n]+
+** mov [^\n]+
+** fcvtzun z0\.b, [^\n]+
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z0_z29, svfloat16x2_t, svuint8_t,
+ z0_res = svcvtzn_u8_f16_x2 (z29),
+ z0_res = svcvtzn_u8 (z29))
+
+/*
+** cvtzn_z5_z0:
+** fcvtzun z5\.b, {z0\.h - z1\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z5_z0, svfloat16x2_t, svuint8_t,
+ z5 = svcvtzn_u8_f16_x2 (z0),
+ z5 = svcvtzn_u8 (z0))
+
+/*
+** cvtzn_z22_z16:
+** fcvtzun z22\.b, {z16\.h - z17\.h}
+** ret
+*/
+TEST_X2_NARROW (cvtzn_z22_z16, svfloat16x2_t, svuint8_t,
+ z22 = svcvtzn_u8_f16_x2 (z16),
+ z22 = svcvtzn_u8 (z16))
--
2.43.0
