For the gcc.target/loongarch/bitwise-shift-reassoc-clobber.c,
some extensions are eliminated in ext_dce in commit r16-1835.
This will result in the following rtx being generated in the
combine pass:
(insn 12 10 15 2 (set (reg/v:DI 23 $r23 [ x ])
(sign_extend:DI (plus:SI
(subreg:SI
(and:DI (ashift:DI
(reg/v:DI 23 $r23 [ x ])
(const_int 3 [0x3]))
(const_int 2208 [0x8a0])) 0)
(reg:SI 23 $r23 [ x ]))))
"test.c":7:7 266 {and_alsl_reversesi_extended}
(nil))
However, in the template '<optab>_alsl_reversesi_extended',
operands[0] and operands[4] cannot be assigned to the same hardware
register, which causes ICE during the reload pass.
Now add restrictions on hard registers in template conditions.
gcc/ChangeLog:
* config/loongarch/loongarch.md
(<optab>_alsl_reversesi_extended): Add conditions.
---
gcc/config/loongarch/loongarch.md | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index f7005dee5b6..8c5f9066c5e 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -3174,7 +3174,9 @@ (define_insn_and_split "<optab>_alsl_reversesi_extended"
(match_operand:SI 4 "register_operand" "r"))))]
"TARGET_64BIT
&& loongarch_reassoc_shift_bitwise (<is_and>, operands[2], operands[3],
- SImode)"
+ SImode)
+ && !(GP_REG_P (REGNO (operands[0]))
+ && REGNO (operands[0]) == REGNO (operands[4]))"
"#"
"&& reload_completed"
[; r0 = r1 [&|^] r3 is emitted in PREPARATION-STATEMENTS because we
--
2.34.1
