On Sat, 2025-07-05 at 17:55 +0800, Xi Ruoyao wrote:
> On Sat, 2025-07-05 at 11:20 +0800, Lulu Cheng wrote:
> > For the gcc.target/loongarch/bitwise-shift-reassoc-clobber.c,
> > some extensions are eliminated in ext_dce in commit r16-1835.
> > 
> > This will result in the following rtx being generated in the
> > combine pass:
> > (insn 12 10 15 2 (set (reg/v:DI 23 $r23 [ x ])
> >    (sign_extend:DI (plus:SI
> >                      (subreg:SI
> >                        (and:DI (ashift:DI
> >                                 (reg/v:DI 23 $r23 [ x ])
> >                        (const_int 3 [0x3]))
> >                    (const_int 2208 [0x8a0])) 0)
> >            (reg:SI 23 $r23 [ x ]))))
> >    "test.c":7:7 266 {and_alsl_reversesi_extended}
> >      (nil))
> > 
> > However, in the template '<optab>_alsl_reversesi_extended',
> > operands[0] and operands[4] cannot be assigned to the same hardware
> > register, which causes ICE during the reload pass.
> 
> Oops.  We have:
> 
> Trying 10 -> 12: 
>    10: r91:DI=sign_extend($r23:DI<<0x3&0x8a0#0+$r23:SI)
>       REG_DEAD $r23:DI
>    12: $r23:DI=r91:DI
>       REG_DEAD r91:DI
> Successfully matched this instruction:
> (set (reg/v:DI 23 $r23 [ x ])
>     (sign_extend:DI (plus:SI (subreg:SI (and:DI (ashift:DI (reg/v:DI
> 23 $r23 [ x ])
>                         (const_int 3 [0x3]))
>                     (const_int 2208 [0x8a0])) 0)
>             (reg:SI 23 $r23 [ x ]))))
> allowing combination of insns 10 and 12
> 
> But the instruction description already has earlyclobber:
> 
>   [(set (match_operand:DI 0 "register_operand" "=&r")
>         (sign_extend:DI
>           (plus:SI
>             (subreg:SI
>               (any_bitwise:DI
>                 (ashift:DI
>                   (match_operand:DI 1 "register_operand" "r0")
>                   (match_operand:SI 2 "const_immalsl_operand" ""))
>                 (match_operand:DI 3 "const_int_operand" "i"))
>               0)
>             (match_operand:SI 4 "register_operand" "r"))))]
> 
> To me if we need to "fix up" this in our machine description we'd need
> to check REGNO everywhere we have an earlyclobber.
> 
> So Jeff & Richard: shouldn't combine simply reject those cases where
> substitute a hard register in would violate the earlyclobber?

Possibly this is https://gcc.gnu.org/PR101882.  Specifically comment 5
from Segher:

"The LRA change is correct AFAICS.  But combine makes a change that
violates the earlyclobber...  I need to do something about that, too."

-- 
Xi Ruoyao <xry...@xry111.site>

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