On Sat, 2025-07-05 at 11:20 +0800, Lulu Cheng wrote:
> For the gcc.target/loongarch/bitwise-shift-reassoc-clobber.c,
> some extensions are eliminated in ext_dce in commit r16-1835.
>
> This will result in the following rtx being generated in the
> combine pass:
> (insn 12 10 15 2 (set (reg/v:DI 23 $r23 [ x ])
> (sign_extend:DI (plus:SI
> (subreg:SI
> (and:DI (ashift:DI
> (reg/v:DI 23 $r23 [ x ])
> (const_int 3 [0x3]))
> (const_int 2208 [0x8a0])) 0)
> (reg:SI 23 $r23 [ x ]))))
> "test.c":7:7 266 {and_alsl_reversesi_extended}
> (nil))
>
> However, in the template '<optab>_alsl_reversesi_extended',
> operands[0] and operands[4] cannot be assigned to the same hardware
> register, which causes ICE during the reload pass.
Oops. We have:
Trying 10 -> 12:
10: r91:DI=sign_extend($r23:DI<<0x3&0x8a0#0+$r23:SI)
REG_DEAD $r23:DI
12: $r23:DI=r91:DI
REG_DEAD r91:DI
Successfully matched this instruction:
(set (reg/v:DI 23 $r23 [ x ])
(sign_extend:DI (plus:SI (subreg:SI (and:DI (ashift:DI (reg/v:DI 23 $r23 [
x ])
(const_int 3 [0x3]))
(const_int 2208 [0x8a0])) 0)
(reg:SI 23 $r23 [ x ]))))
allowing combination of insns 10 and 12
But the instruction description already has earlyclobber:
[(set (match_operand:DI 0 "register_operand" "=&r")
(sign_extend:DI
(plus:SI
(subreg:SI
(any_bitwise:DI
(ashift:DI
(match_operand:DI 1 "register_operand" "r0")
(match_operand:SI 2 "const_immalsl_operand" ""))
(match_operand:DI 3 "const_int_operand" "i"))
0)
(match_operand:SI 4 "register_operand" "r"))))]
To me if we need to "fix up" this in our machine description we'd need
to check REGNO everywhere we have an earlyclobber.
So Jeff & Richard: shouldn't combine simply reject those cases where
substitute a hard register in would violate the earlyclobber?
> Now add restrictions on hard registers in template conditions.
>
> gcc/ChangeLog:
>
> * config/loongarch/loongarch.md
> (<optab>_alsl_reversesi_extended): Add conditions.
>
> ---
> gcc/config/loongarch/loongarch.md | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/loongarch/loongarch.md
> b/gcc/config/loongarch/loongarch.md
> index f7005dee5b6..8c5f9066c5e 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -3174,7 +3174,9 @@ (define_insn_and_split "<optab>_alsl_reversesi_extended"
> (match_operand:SI 4 "register_operand" "r"))))]
> "TARGET_64BIT
> && loongarch_reassoc_shift_bitwise (<is_and>, operands[2], operands[3],
> - SImode)"
> + SImode)
> + && !(GP_REG_P (REGNO (operands[0]))
> + && REGNO (operands[0]) == REGNO (operands[4]))"
> "#"
> "&& reload_completed"
> [; r0 = r1 [&|^] r3 is emitted in PREPARATION-STATEMENTS because we
--
Xi Ruoyao <xry...@xry111.site>
