[COMMITTED 1/2] RISC-V: prefetch: const offset needs to have 5 bits zero, not 4

[Vineet Gupta]

Spotted this by chance as I saw a similar fixup in comment.
>From comments, I think this is needed, but I've not hit any issues due
to this.

gcc/ChangeLog:

        * config/riscv/predicates.md (prefetch_operand): mack 5 bits.

Signed-off-by: Vineet Gupta <vine...@rivosinc.com>
---
 gcc/config/riscv/predicates.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 061904b6e000..8baad2fae7a9 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -33,11 +33,11 @@ (define_predicate "arith_operand"
 (define_predicate "prefetch_operand"
   (ior (match_operand 0 "register_operand")
        (and (match_test "const_arith_operand (op, VOIDmode)")
-           (match_test "(INTVAL (op) & 0xf) == 0"))
+           (match_test "(INTVAL (op) & 0x1f) == 0"))
        (and (match_code "plus")
            (match_test "register_operand (XEXP (op, 0), word_mode)")
            (match_test "const_arith_operand (XEXP (op, 1), VOIDmode)")
-           (match_test "(INTVAL (XEXP (op, 1)) & 0xf) == 0"))))
+           (match_test "(INTVAL (XEXP (op, 1)) & 0x1f) == 0"))))
 
 (define_predicate "lui_operand"
   (and (match_code "const_int")
-- 
2.43.0