From: Pan Li <pan2...@intel.com>
Add asm dump check and run test for vec_duplicate + vsub.vv
combine to vsub.vx.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for vsub.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 392 ++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c | 8 +
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c | 8 +
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c | 8 +
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c | 8 +
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c | 8 +
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c | 8 +
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c | 8 +
.../riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c | 8 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-i16.c | 14 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-i32.c | 14 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-i64.c | 14 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-i8.c | 14 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u16.c | 14 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u32.c | 14 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u64.c | 14 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u8.c | 14 +
17 files changed, 568 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 11a32cbbf0f..c9ea22800c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -398,4 +398,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, vadd)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { 127 },
+ {
+ 127, 127, 127, 127,
+ 126, 126, 126, 126,
+ -1, -1, -1, -1,
+ 125, 125, 125, 125,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -128, -128, -128, -128,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { -128 },
+ {
+ -128, -128, -128, -128,
+ -127, -127, -127, -127,
+ -1, -1, -1, -1,
+ -126, -126, -126, -126,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 127, 127, 127, 127,
+ 2, 2, 2, 2,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { 32767 },
+ {
+ 32767, 32767, 32767, 32767,
+ 32766, 32766, 32766, 32766,
+ -1, -1, -1, -1,
+ 32765, 32765, 32765, 32765,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -32768, -32768, -32768, -32768,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { -32768 },
+ {
+ -32768, -32768, -32768, -32768,
+ -32767, -32767, -32767, -32767,
+ -1, -1, -1, -1,
+ -32766, -32766, -32766, -32766,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 32767, 32767, 32767, 32767,
+ 2, 2, 2, 2,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { 2147483647 },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483646, 2147483646, 2147483646, 2147483646,
+ -1, -1, -1, -1,
+ 2147483645, 2147483645, 2147483645, 2147483645,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { -2147483648 },
+ {
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ -2147483647, -2147483647, -2147483647, -2147483647,
+ -1, -1, -1, -1,
+ -2147483646, -2147483646, -2147483646, -2147483646,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2, 2, 2, 2,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ -1, -1, -1, -1,
+ -2, -2, -2, -2,
+ },
+ },
+ {
+ { 9223372036854775807ll },
+ {
+ 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll,
9223372036854775807ll,
+ 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll,
9223372036854775806ll,
+ -1, -1, -1,
-1,
+ 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll,
9223372036854775805ll,
+ },
+ {
+ 0, 0,
0, 0,
+ -1, -1,
-1, -1,
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ -2, -2,
-2, -2,
+ },
+ },
+ {
+ { -9223372036854775808ull },
+ {
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ -9223372036854775807ll, -9223372036854775807ll,
-9223372036854775807ll, -9223372036854775807ll,
+ -1, -1,
-1, -1,
+ -9223372036854775806ll, -9223372036854775806ll,
-9223372036854775806ll, -9223372036854775806ll,
+ },
+ {
+ 0, 0, 0,
0,
+ 1, 1, 1,
1,
+ 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll,
9223372036854775807ll,
+ 2, 2, 2,
2,
+ },
+ },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 11, 11, 11, 11,
+ 9, 9, 9, 9,
+ },
+ },
+ {
+ { 127 },
+ {
+ 127, 127, 127, 127,
+ 128, 128, 128, 128,
+ 254, 254, 254, 254,
+ 255, 255, 255, 255,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 127, 127, 127, 127,
+ 128, 128, 128, 128,
+ },
+ },
+ {
+ { 253 },
+ {
+ 253, 253, 253, 253,
+ 254, 254, 254, 254,
+ 255, 255, 255, 255,
+ 252, 252, 252, 252,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 255, 255, 255, 255,
+ },
+ },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 11, 11, 11, 11,
+ 9, 9, 9, 9,
+ },
+ },
+ {
+ { 32767 },
+ {
+ 32767, 32767, 32767, 32767,
+ 32768, 32768, 32768, 32768,
+ 65534, 65534, 65534, 65534,
+ 65535, 65535, 65535, 65535,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 32767, 32767, 32767, 32767,
+ 32768, 32768, 32768, 32768,
+ },
+ },
+ {
+ { 65533 },
+ {
+ 65533, 65533, 65533, 65533,
+ 65534, 65534, 65534, 65534,
+ 65535, 65535, 65535, 65535,
+ 65532, 65532, 65532, 65532,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 65535, 65535, 65535, 65535,
+ },
+ },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 11, 11, 11, 11,
+ 9, 9, 9, 9,
+ },
+ },
+ {
+ { 2147483647 },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483648, 2147483648, 2147483648, 2147483648,
+ 4294967294, 4294967294, 4294967294, 4294967294,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483648, 2147483648, 2147483648, 2147483648,
+ },
+ },
+ {
+ { 4294967293 },
+ {
+ 4294967293, 4294967293, 4294967293, 4294967293,
+ 4294967294, 4294967294, 4294967294, 4294967294,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967292, 4294967292, 4294967292, 4294967292,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, vsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 11, 11, 11, 11,
+ 9, 9, 9, 9,
+ },
+ },
+ {
+ { 9223372036854775807ull },
+ {
+ 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull,
+ 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,
9223372036854775808ull,
+ 18446744073709551614ull, 18446744073709551614ull,
18446744073709551614ull, 18446744073709551614ull,
+ 18446744073709551615ull, 18446744073709551615ull,
18446744073709551615ull, 18446744073709551615ull,
+ },
+ {
+ 0, 0, 0,
0,
+ 1, 1, 1,
1,
+ 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull,
+ 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,
9223372036854775808ull,
+ },
+ },
+ {
+ { 18446744073709551613ull },
+ {
+ 18446744073709551613ull, 18446744073709551613ull,
18446744073709551613ull, 18446744073709551613ull,
+ 18446744073709551614ull, 18446744073709551614ull,
18446744073709551614ull, 18446744073709551614ull,
+ 18446744073709551615ull, 18446744073709551615ull,
18446744073709551615ull, 18446744073709551615ull,
+ 18446744073709551612ull, 18446744073709551612ull,
18446744073709551612ull, 18446744073709551612ull,
+ },
+ {
+ 0, 0,
0, 0,
+ 1, 1,
1, 1,
+ 2, 2,
2, 2,
+ 18446744073709551615ull, 18446744073709551615ull,
18446744073709551615ull, 18446744073709551615ull,
+ },
+ },
+};
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c
new file mode 100644
index 00000000000..684ede28996
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int16_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c
new file mode 100644
index 00000000000..4f0f03e7ff0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int32_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c
new file mode 100644
index 00000000000..ace4021af2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int64_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c
new file mode 100644
index 00000000000..e8513b552cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int8_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c
new file mode 100644
index 00000000000..cfcbac08aaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint16_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c
new file mode 100644
index 00000000000..726713ca5f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint32_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c
new file mode 100644
index 00000000000..67e777025a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint64_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c
new file mode 100644
index 00000000000..d1441164d7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint8_t, -)
+
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c
new file mode 100644
index 00000000000..445835d2a85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c
new file mode 100644
index 00000000000..114d2172694
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c
new file mode 100644
index 00000000000..ecbefe777b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c
new file mode 100644
index 00000000000..4dd66429280
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c
new file mode 100644
index 00000000000..96d8be53e37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint16_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c
new file mode 100644
index 00000000000..aea3ef40290
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint32_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c
new file mode 100644
index 00000000000..aec9dde4764
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint64_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c
new file mode 100644
index 00000000000..13741f9a681
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint8_t
+
+DEF_VX_BINARY_CASE_0_WRAP(T, -)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vsub)
+#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n)
+
+#include "vx_binary_run.h"
--
2.43.0
