[PATCH v1 6/7] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1

Sun, 11 May 2025 18:23:26 -0700 

From: Pan Li <pan2...@intel.com>

Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c: New test.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c    | 8 ++++++++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c    | 8 ++++++++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c    | 8 ++++++++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c     | 8 ++++++++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c    | 8 ++++++++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c    | 8 ++++++++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c    | 8 ++++++++
 .../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c     | 8 ++++++++
 8 files changed, 64 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c
new file mode 100644
index 00000000000..ac209e7f884
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int16_t, -, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c
new file mode 100644
index 00000000000..afb852b18f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int32_t, -, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c
new file mode 100644
index 00000000000..713f746123c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int64_t, -, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c
new file mode 100644
index 00000000000..18a098cdda1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(int8_t, -, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c
new file mode 100644
index 00000000000..8da3ac356ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint16_t, -, VX_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c
new file mode 100644
index 00000000000..f8fdcaad34a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint32_t, -, VX_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c
new file mode 100644
index 00000000000..ddfc1068c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint64_t, -, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c
new file mode 100644
index 00000000000..ede60c263f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_1(uint8_t, -, VX_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler {vsub.vx} } } */
-- 
2.43.0

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