From: Pan Li <pan2...@intel.com>
Add asm dump check test for vec_duplicate + vsub.vv combine to vsub.vx.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c | 8 ++++++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c | 8 ++++++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c | 8 ++++++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c | 8 ++++++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c | 8 ++++++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c | 8 ++++++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c | 8 ++++++++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c | 8 ++++++++
8 files changed, 64 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c
new file mode 100644
index 00000000000..7a252a922aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int16_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c
new file mode 100644
index 00000000000..02543446720
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int32_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c
new file mode 100644
index 00000000000..fc01c5479b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int64_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c
new file mode 100644
index 00000000000..6da427130f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int8_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c
new file mode 100644
index 00000000000..aab9b9b8177
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint16_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c
new file mode 100644
index 00000000000..01e159e98d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint32_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c
new file mode 100644
index 00000000000..5fa8a2be503
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint64_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c
new file mode 100644
index 00000000000..2a06880ec23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
+
+#include "vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(uint8_t, -)
+
+/* { dg-final { scan-assembler-not {vsub.vx} } } */
--
2.43.0
