From: Pan Li <pan2...@intel.com> This patch would like to introduce the combine of vec_dup + vsub.vv into vsub.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15 in test. There will be two cases for the combine:
Case 0: | ... | vmv.v.x | L1: | vsub.vv | J L1 | ... Case 1: | ... | L1: | vmv.v.x | vsub.vv | J L1 | ... Both will be combined to below if the cost of GR2VR is zero. | ... | L1: | vsub.vx | J L1 | ... The below test suites are passed for this patch series. * The rv64gcv fully regression test. Pan Li (7): RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2 gcc/config/riscv/autovec-opt.md | 17 + gcc/config/riscv/riscv.cc | 1 + gcc/config/riscv/vector-iterators.md | 2 +- .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 392 ++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-i16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-i32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-i64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-i8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-u16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-u32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-u64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-2-u8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-i16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-i32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-i64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-i8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-u16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-u32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-u64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-4-u8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-i16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-i32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-i64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-i8.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-u16.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-u32.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-u64.c | 8 + .../riscv/rvv/autovec/vx_vf/vx_vsub-6-u8.c | 8 + .../rvv/autovec/vx_vf/vx_vsub-run-1-i16.c | 14 + .../rvv/autovec/vx_vf/vx_vsub-run-1-i32.c | 14 + .../rvv/autovec/vx_vf/vx_vsub-run-1-i64.c | 14 + .../rvv/autovec/vx_vf/vx_vsub-run-1-i8.c | 14 + .../rvv/autovec/vx_vf/vx_vsub-run-1-u16.c | 14 + .../rvv/autovec/vx_vf/vx_vsub-run-1-u32.c | 14 + .../rvv/autovec/vx_vf/vx_vsub-run-1-u64.c | 14 + .../rvv/autovec/vx_vf/vx_vsub-run-1-u8.c | 14 + 60 files changed, 907 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-1-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-2-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-3-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-4-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-5-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-6-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c -- 2.43.0
