> > Thank you very much for your professional reply. I am trying to solve the > > problem > > using the "spec_restriction" way. But unfortunately, I have a new problem. > > As > > pattern below, how can I enable "r" and disable "K" when XTheadVector? "rK" > > already > > seems to be the smallest unit and not able to be > > controlled separately using spec_restriction? > > > > (define_insn "@pred_madc<mode>" > > [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr") > > (unspec:<VM> > > [(plus:VI > > (match_operand:VI 1 "register_operand" " %0, vr, vr") > > (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi")) > > (match_operand:<VM> 3 "register_operand" " vm, vm, vm") > > (unspec:<VM> > > [(match_operand 4 "vector_length_operand" " rK, rK, rK") > > (match_operand 5 "const_int_operand" " i, i, i") > > (reg:SI VL_REGNUM) > > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))] > > "TARGET_VECTOR" > > "vmadc.v%o2m\t%0,%1,%v2,%3" > > [(set_attr "type" "vicalu") > > (set_attr "mode" "<MODE>") > > (set_attr "vl_op_idx" "4") > > (set (attr "avl_type_idx") (const_int 5)) > > (set_attr "spec_restriction" "thv,none,none")]) > > "rK" can be split up further into "r" and "K" so I'd say you > need to adjust (and split) the alternatives accordingly. The new "r" > alternative would have spec_restriction "none" and the "K" alternative "rvv".
Yes. This will solve the problem, but it will lead to very large-scale changes (splitting each rK, adding 1 column constraint), and make the pattern more complex and more difficult to maintain. In contrast, how about replacing "rK" with a new constrain in the way jeff mentioned? For example, "Vvl". Jeff: We could also create a new constraint that mostly behaves like rK, but rejects (const_int 1) when thead-vector is enabled and use that in the vsetvl pattern instead of rK. ( https://gcc.gnu.org/pipermail/gcc-patches/2024-December/671836.html ) BR Jin > -- > Regards > Robin
