> > Looking at the log for the reload pass, it is found that "Changing pseudo 
> > 209
> > in operand 3 of insn 69 on equiv 0x 1". It converts the vl operand in insn
> > from the expected register(reg:DI 209) to the constant 1(const_int 1 [0x1]).
> >
> > This conversion occurs because, although the predicate for the vl operand is
> > restricted by "vector_length_operand" in the pattern, the constraint is 
> > still
> > "rK", which allows the transformation.
> >
> > The issue is that changing the "rK" constraint to "rJ" for the constraint of
> > vl operand in the pattern would prevent this conversion, But unfortunately
> > this will conflict with RVV (RISC-V Vector Extension).
> >
> > This is why I initially considered using UNSPEC to address the XTheadVector
> > problem while minimizing interference with RVV.
> >
> > I'm not sure if there is a better way, do you have any suggestions?
> 
> We'd probably need to disable the alternatives via the "spec_restriction"
> attribute as we do for the fma ops.

Hi, Robin
Thank you very much for your professional reply. I am trying to solve the 
problem
using the "spec_restriction" way. But unfortunately, I have a new problem. As
pattern below, how can I enable "r" and disable "K" when XTheadVector? "rK" 
already
seems to be the smallest unit and not able to be
controlled separately using spec_restriction?

(define_insn "@pred_madc<mode>"
  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr, &vr")
        (unspec:<VM>
           [(plus:VI
             (match_operand:VI 1 "register_operand"     "  %0,  vr,  vr")
             (match_operand:VI 2 "vector_arith_operand" "vrvi,  vr,  vi"))
            (match_operand:<VM> 3 "register_operand"    "  vm,  vm,  vm")
            (unspec:<VM>
              [(match_operand 4 "vector_length_operand" "  rK,  rK,  rK")
               (match_operand 5 "const_int_operand"     "   i,   i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
  "TARGET_VECTOR"
  "vmadc.v%o2m\t%0,%1,%v2,%3"
  [(set_attr "type" "vicalu")
   (set_attr "mode" "<MODE>")
   (set_attr "vl_op_idx" "4")
   (set (attr "avl_type_idx") (const_int 5))
   (set_attr "spec_restriction" "thv,none,none")])
  
BR
Jin

> --
> Regards
> Robin
> 

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