> > --- a/gcc/config/riscv/riscv-vector-builtins.cc
> > +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> > @@ -4089,7 +4089,23 @@ function_expander::add_input_operand (unsigned argno)
> > {
> > tree arg = CALL_EXPR_ARG (exp, argno);
> > rtx x = expand_normal (arg);
> > - add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x);
> > +
> > + /* Since the parameter vl of XTheadVector does not support
> > + immediate numbers, we need to put it in the register
> > + in advance. */
> > + if (TARGET_XTHEADVECTOR
> > + && CONST_INT_P (x)
> > + && base->apply_vl_p ()
> > + && argno == (unsigned) (call_expr_nargs (exp) - 1)
> > + && x != CONST0_RTX (GET_MODE (x)))
> > + {
> > + rtx tmp = gen_reg_rtx (word_mode);
> > + /* Use UNSPEC to avoid being optimized before vsetvl pass. */
> > + emit_insn (gen_th_pred_vl_mov (word_mode, tmp, x));
> > + add_input_operand (TYPE_MODE (TREE_TYPE (arg)), tmp);
> > + }
> > + else
> > + add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x);
> > }
> So I would just do:
>
>
> tmp = force_reg (word_mode, x);
> add_input_operand (TYPE_MODE (TREE_TYPE (arg)), tmp);
>
> In the thead specific code. That generates the initial code correctly.
> At that point we just need to make sure nothing like combine, cprop, etc
> propagates the constant into the vsetvl. The way to prevent that is
> with the operand predicates on the vsetvl insns.
>
>
> jeff
Hi, jeff
I missed some information because of the long time.
As I said before, instead of using UNSPEC, In the curr_insn_transform function,
the insn is transformed from:
(insn 69 67 225 12 (set (mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128]
A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(reg:DI 209)
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 143 [ _xx ])
(mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0 S[128, 128] A32])))
"pr116593.C":14:24 discrim 1 3883 {pred_storervvm8sf}
(expr_list:REG_DEAD (reg/v:RVVM8SF 143 [ _xx ])
(nil)))
to
(insn 69 284 225 11 (set (mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0
S[128, 128] A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(const_int 1 [0x1])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 104 v8 [orig:143 _xx ] [143])
(mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0 S[128, 128]
A32]))) "pr116593.C":14:24 discrim 1 3883 {pred_storervvm8sf}
(nil))
Looking at the log for the reload pass, it is found that "Changing pseudo 209
in operand 3 of insn 69 on equiv 0x 1".
It converts the vl operand in insn from the expected register(reg:DI 209) to
the constant 1(const_int 1 [0x1]).
This conversion occurs because, although the predicate for the vl operand is
restricted by "vector_length_operand" in the pattern,
the constraint is still "rK", which allows the transformation.
The issue is that changing the "rK" constraint to "rJ" for the constraint of vl
operand in the pattern would prevent this conversion,
But unfortunately this will conflict with RVV (RISC-V Vector Extension).
This is why I initially considered using UNSPEC to address the XTheadVector
problem while minimizing interference with RVV.
I'm not sure if there is a better way, do you have any suggestions?
BR
Jin
