> Looking at the log for the reload pass, it is found that "Changing pseudo 209 > in operand 3 of insn 69 on equiv 0x 1". It converts the vl operand in insn > from the expected register(reg:DI 209) to the constant 1(const_int 1 [0x1]). > > This conversion occurs because, although the predicate for the vl operand is > restricted by "vector_length_operand" in the pattern, the constraint is still > "rK", which allows the transformation. > > The issue is that changing the "rK" constraint to "rJ" for the constraint of > vl operand in the pattern would prevent this conversion, But unfortunately > this will conflict with RVV (RISC-V Vector Extension). > > This is why I initially considered using UNSPEC to address the XTheadVector > problem while minimizing interference with RVV. > > I'm not sure if there is a better way, do you have any suggestions?
We'd probably need to disable the alternatives via the "spec_restriction" attribute as we do for the fma ops. -- Regards Robin
