https://gcc.gnu.org/g:b074b25e8adb20924a23427c74b19aae2b5f0f99
commit b074b25e8adb20924a23427c74b19aae2b5f0f99
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Nov 15 23:34:27 2024 -0500
Revert changes
Diff:
---
gcc/config.gcc | 4 +-
gcc/config/rs6000/aix71.h | 1 -
gcc/config/rs6000/aix72.h | 1 -
gcc/config/rs6000/aix73.h | 1 -
gcc/config/rs6000/driver-rs6000.cc | 2 -
gcc/config/rs6000/power10.md | 144 ++++++++++++++--------------
gcc/config/rs6000/rs6000-c.cc | 2 -
gcc/config/rs6000/rs6000-cpus.def | 7 --
gcc/config/rs6000/rs6000-opts.h | 1 -
gcc/config/rs6000/rs6000-tables.opt | 11 +--
gcc/config/rs6000/rs6000.cc | 28 ++----
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 6 --
gcc/testsuite/gcc.target/powerpc/future-1.c | 13 ---
gcc/testsuite/gcc.target/powerpc/future-2.c | 24 -----
16 files changed, 87 insertions(+), 161 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index d45d1faba7a0..9b616bd6e1f8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -541,7 +541,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5649,7 +5649,7 @@ case "${target}" in
tm_defines="${tm_defines} CONFIG_PPC405CR"
eval "with_$which=405"
;;
- "" | common | native | future \
+ "" | common | native \
| power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 505986b33d63..4350dcd89524 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 242ca94bd065..fe59f8319b48 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 2bd6b4bb3c4f..1318b0b3662d 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 57199b3172f1..a054827b2e03 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -453,7 +453,6 @@ static const struct asm_name asm_names[] = {
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
{ "power11", "-mpwr11" },
- { "future", "-mfuture" },
{ "powerpc", "-mppc" },
{ "rs64", "-mppc" },
{ "603", "-m603" },
@@ -483,7 +482,6 @@ static const struct asm_name asm_names[] = {
{ "power9", "-mpower9" },
{ "power10", "-mpower10" },
{ "power11", "-mpower11" },
- { "future", "-mfuture" },
{ "a2", "-ma2" },
{ "powerpc", "-mppc" },
{ "powerpc64", "-mppc64" },
diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index e42b057dc45b..2310c4603457 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,4 +1,4 @@
-;; Scheduling description for the IBM Power10, Power11, and Future processors.
+;; Scheduling description for the IBM Power10 and Power11 processors.
;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthau...@us.ibm.com).
@@ -97,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
(define_insn_reservation "power10-fused-load" 4
(and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-prefixed-load" 4
@@ -110,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-load-update" 4
(and (eq_attr "type" "load")
(eq_attr "update" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-fpload-double" 4
@@ -124,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
(define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -132,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-fpload-update-double" 4
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -148,27 +148,27 @@
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-fpload-update-single" 7
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-vecload" 4
(and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
; lxvp
(define_insn_reservation "power10-vecload-pair" 4
(and (eq_attr "type" "vecload")
(eq_attr "size" "256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
; Store Unit
@@ -178,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
(define_insn_reservation "power10-fused-store" 0
(and (eq_attr "type" "fused_store_store")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
(define_insn_reservation "power10-prefixed-store" 0
@@ -191,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
; Update forms have 2 cycle latency for updated addr reg
(define_insn_reservation "power10-store-update" 2
(and (eq_attr "type" "store,fpstore")
(eq_attr "update" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
; stxvp
(define_insn_reservation "power10-vecstore-pair" 0
(and (eq_attr "type" "vecstore")
(eq_attr "size" "256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,stu0_power10+stu1_power10")
(define_insn_reservation "power10-larx" 4
(and (eq_attr "type" "load_l")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
; All load quad forms
(define_insn_reservation "power10-lq" 4
(and (eq_attr "type" "load,load_l")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-stcx" 0
(and (eq_attr "type" "store_c")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
; All store quad forms
(define_insn_reservation "power10-stq" 0
(and (eq_attr "type" "store,store_c")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,stu0_power10+stu1_power10")
(define_insn_reservation "power10-sync" 1
(and (eq_attr "type" "sync,isync")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
@@ -248,7 +248,7 @@
(define_insn_reservation "power10-alu" 2
(and (eq_attr "type" "add,exts,integer,logical,isel")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 4 cycle CR latency
(define_bypass 4 "power10-alu"
@@ -256,28 +256,28 @@
(define_insn_reservation "power10-fused_alu" 2
(and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; paddi
(define_insn_reservation "power10-paddi" 2
(and (eq_attr "type" "add")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; Rotate/shift (non-record form)
(define_insn_reservation "power10-rot" 2
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; Record form rotate/shift
(define_insn_reservation "power10-rot-compare" 3
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 5 cycle CR latency
(define_bypass 5 "power10-rot-compare"
@@ -285,7 +285,7 @@
(define_insn_reservation "power10-alu2" 3
(and (eq_attr "type" "cntlz,popcnt,trap")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 5 cycle CR latency
(define_bypass 5 "power10-alu2"
@@ -293,24 +293,24 @@
(define_insn_reservation "power10-cmp" 2
(and (eq_attr "type" "cmp")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; Treat 'two' and 'three' types as 2 or 3 way cracked
(define_insn_reservation "power10-two" 4
(and (eq_attr "type" "two")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-three" 6
(and (eq_attr "type" "three")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_all_power10,EXU_power10")
(define_insn_reservation "power10-mul" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 4 cycle MUL->MUL latency
(define_bypass 4 "power10-mul"
@@ -319,7 +319,7 @@
(define_insn_reservation "power10-mul-compare" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; 4 cycle MUL->MUL latency
(define_bypass 4 "power10-mul-compare"
@@ -331,13 +331,13 @@
(define_insn_reservation "power10-div" 12
(and (eq_attr "type" "div")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-div-compare" 12
(and (eq_attr "type" "div")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; 14 cycle CR latency
(define_bypass 14 "power10-div-compare"
@@ -345,34 +345,34 @@
(define_insn_reservation "power10-crlogical" 2
(and (eq_attr "type" "cr_logical")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfcrf" 2
(and (eq_attr "type" "mfcrf")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfcr" 3
(and (eq_attr "type" "mfcr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; Should differentiate between 1 cr field and > 1 since target of > 1 cr
; is cracked
(define_insn_reservation "power10-mtcr" 3
(and (eq_attr "type" "mtcr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mtjmpr" 3
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -380,126 +380,126 @@
(define_insn_reservation "power10-fpsimple" 3
(and (eq_attr "type" "fpsimple")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fp" 5
(and (eq_attr "type" "fp,dmul")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fpcompare" 3
(and (eq_attr "type" "fpcompare")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-sdiv" 22
(and (eq_attr "type" "sdiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-ddiv" 27
(and (eq_attr "type" "ddiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-sqrt" 26
(and (eq_attr "type" "ssqrt")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-dsqrt" 36
(and (eq_attr "type" "dsqrt")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vec-2cyc" 2
(and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fused-vec" 2
(and (eq_attr "type" "fused_vector")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-veccmp" 3
(and (eq_attr "type" "veccmp")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecsimple" 2
(and (eq_attr "type" "vecsimple")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecnormal" 5
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qp" 12
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "prefixed" "no")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecperm-compare" 3
(and (eq_attr "type" "vecperm")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-prefixed-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-veccomplex" 6
(and (eq_attr "type" "veccomplex")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecfdiv" 24
(and (eq_attr "type" "vecfdiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecdiv" 27
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qpdiv" 56
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qpmul" 24
(and (eq_attr "type" "qmul")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mtvsr" 2
(and (eq_attr "type" "mtvsr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfvsr" 2
(and (eq_attr "type" "mfvsr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -507,26 +507,26 @@
; Branch is 2 cycles, grouped with STU for issue
(define_insn_reservation "power10-branch" 2
(and (eq_attr "type" "jmpreg,branch")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
(define_insn_reservation "power10-fused-branch" 3
(and (eq_attr "type" "fused_mtbc")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
; Crypto
(define_insn_reservation "power10-crypto" 4
(and (eq_attr "type" "crypto")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; HTM
(define_insn_reservation "power10-htm" 2
(and (eq_attr "type" "htmsimple,htm")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -535,26 +535,26 @@
(define_insn_reservation "power10-dfp" 12
(and (eq_attr "type" "dfp")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-dfpq" 12
(and (eq_attr "type" "dfp")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; MMA
(define_insn_reservation "power10-mma" 9
(and (eq_attr "type" "mma")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_super_power10")
(define_insn_reservation "power10-prefixed-mma" 9
(and (eq_attr "type" "mma")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_super_power10")
; 4 cycle MMA->MMA latency
(define_bypass 4 "power10-mma,power10-prefixed-mma"
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index b0b5701c7fa9..4dc80e598fa4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -438,8 +438,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
if ((flags & OPTION_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
- if ((flags & OPTION_MASK_FUTURE) != 0)
- rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 62e6c9d3b589..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -89,10 +89,6 @@
#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
| OPTION_MASK_POWER11)
-#define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER \
- | OPTION_MASK_FUTURE \
- | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
-
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -121,7 +117,6 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
- | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
@@ -130,7 +125,6 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
- | OPTION_MASK_FUTURE \
| OPTION_MASK_POWER10 \
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
@@ -261,7 +255,6 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 |
ISA_3_0_MASKS_SERVER
| OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 |
ISA_3_1_MASKS_SERVER)
RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
POWER11_MASKS_SERVER)
-RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | FUTURE_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
| MASK_POWERPC64)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index c25ddf92858c..88e357835a5c 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -63,7 +63,6 @@ enum processor_type
PROCESSOR_POWER9,
PROCESSOR_POWER10,
PROCESSOR_POWER11,
- PROCESSOR_FUTURE,
PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
diff --git a/gcc/config/rs6000/rs6000-tables.opt
b/gcc/config/rs6000/rs6000-tables.opt
index fc187c641f8d..a5649fef1ece 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -189,17 +189,14 @@ EnumValue
Enum(rs6000_cpu_opt_value) String(power11) Value(53)
EnumValue
-Enum(rs6000_cpu_opt_value) String(future) Value(54)
+Enum(rs6000_cpu_opt_value) String(powerpc) Value(54)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc) Value(55)
+Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56)
+Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56)
EnumValue
-Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57)
-
-EnumValue
-Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
+Enum(rs6000_cpu_opt_value) String(rs64) Value(57)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 9fd315c6fa08..2b185165610f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1068,7 +1068,7 @@ struct processor_costs power9_cost = {
COSTS_N_INSNS (3), /* SF->DF convert */
};
-/* Instruction costs on Power10/Power11/future processors. */
+/* Instruction costs on Power10/Power11 processors. */
static const
struct processor_costs power10_cost = {
COSTS_N_INSNS (2), /* mulsi */
@@ -4388,8 +4388,7 @@ rs6000_option_override_internal (bool global_init_p)
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
{
if (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
else
rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
@@ -4419,7 +4418,6 @@ rs6000_option_override_internal (bool global_init_p)
&& rs6000_tune != PROCESSOR_POWER9
&& rs6000_tune != PROCESSOR_POWER10
&& rs6000_tune != PROCESSOR_POWER11
- && rs6000_tune != PROCESSOR_FUTURE
&& rs6000_tune != PROCESSOR_PPCA2
&& rs6000_tune != PROCESSOR_CELL
&& rs6000_tune != PROCESSOR_PPC476);
@@ -4435,7 +4433,6 @@ rs6000_option_override_internal (bool global_init_p)
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_PPCE500MC
|| rs6000_tune == PROCESSOR_PPCE500MC64
|| rs6000_tune == PROCESSOR_PPCE5500
@@ -4736,7 +4733,6 @@ rs6000_option_override_internal (bool global_init_p)
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
rs6000_cost = &power10_cost;
break;
@@ -10160,7 +10156,6 @@ rs6000_reassociation_width (unsigned int opc
ATTRIBUTE_UNUSED,
case PROCESSOR_POWER9:
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
if (DECIMAL_FLOAT_MODE_P (mode))
return 1;
if (VECTOR_MODE_P (mode))
@@ -18248,8 +18243,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
/* Separate a load from a narrower, dependent store. */
if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (PATTERN (dep_insn)) == SET
&& MEM_P (XEXP (PATTERN (insn), 1))
@@ -18289,7 +18283,6 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_CELL)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0))
@@ -18865,7 +18858,6 @@ rs6000_issue_rate (void)
return 6;
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
return 8;
default:
return 1;
@@ -19581,11 +19573,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED,
int sched_verbose,
if (rs6000_tune == PROCESSOR_POWER6)
load_store_pendulum = 0;
- /* Do Power10/Power11/future dependent reordering. */
+ /* Do Power10/Power11 dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE))
+ || rs6000_tune == PROCESSOR_POWER11))
power10_sched_reorder (ready, n_ready - 1);
return rs6000_issue_rate ();
@@ -19609,11 +19600,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose,
rtx_insn **ready,
&& recog_memoized (last_scheduled_insn) >= 0)
return power9_sched_reorder2 (ready, *pn_ready - 1);
- /* Do Power10/Power11/future dependent reordering. */
+ /* Do Power10/Power11 dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE))
+ || rs6000_tune == PROCESSOR_POWER11))
return power10_sched_reorder (ready, *pn_ready - 1);
return cached_can_issue_more;
@@ -22831,8 +22821,7 @@ rs6000_register_move_cost (machine_mode mode,
out to be a nop. */
if (rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
else
ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
@@ -24502,7 +24491,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
- { "future", OPTION_MASK_FUTURE, false, false },
{ "power10", OPTION_MASK_POWER10, false, true },
{ "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index daf1a1d41e8c..3d55e078df0b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -101,7 +101,6 @@
you make changes here, make them also there. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpower11; \
mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d266f93ff2e4..0479c062dba6 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -364,7 +364,7 @@
ppc750,ppc7400,ppc7450,
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
- power4,power5,power6,power7,power8,power9,power10,power11,future,
+ power4,power5,power6,power7,power8,power9,power10,power11,
rs64a,mpccore,cell,ppca2,titan"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 876b9f0d4afc..94323bd1db26 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -630,12 +630,6 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
-;; Users should not use -mfuture, but we need to use a bit to identify when
-;; the user changes the default cpu via #pragma GCC target("cpu=future")
-;; and then resets it later.
-mfuture
-Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) WarnRemoved
-
; Documented parameters
-param=rs6000-vect-unroll-limit=
diff --git a/gcc/testsuite/gcc.target/powerpc/future-1.c
b/gcc/testsuite/gcc.target/powerpc/future-1.c
deleted file mode 100644
index f1b940d7bebf..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/future-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Basic check to see if the compiler supports -mcpu=future and if it defines
- _ARCH_PWR11. */
-
-#ifndef _ARCH_FUTURE
-#error "-mcpu=future is not supported"
-#endif
-
-void foo (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/future-2.c
b/gcc/testsuite/gcc.target/powerpc/future-2.c
deleted file mode 100644
index 5552cefa3c2e..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/future-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2" } */
-
-/* Check if we can set the future target via a target attribute. */
-
-__attribute__((__target__("cpu=power9")))
-void foo_p9 (void)
-{
-}
-
-__attribute__((__target__("cpu=power10")))
-void foo_p10 (void)
-{
-}
-
-__attribute__((__target__("cpu=power11")))
-void foo_p11 (void)
-{
-}
-
-__attribute__((__target__("cpu=future")))
-void foo_future (void)
-{
-}
