https://gcc.gnu.org/g:2879c3ba1500ac75a3b8dd17580c885add1aa885
commit 2879c3ba1500ac75a3b8dd17580c885add1aa885
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Nov 15 00:52:20 2024 -0500
Revert changes
Diff:
---
gcc/config/rs6000/rs6000.cc | 129 +++++++++---------------
gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 38 ++-----
gcc/testsuite/gcc.target/powerpc/pr115688.c | 3 +-
3 files changed, 60 insertions(+), 110 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 96603ca61d84..000501ef01d0 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1173,7 +1173,6 @@ const int INSN_NOT_AVAILABLE = -1;
static void rs6000_print_isa_options (FILE *, int, const char *,
HOST_WIDE_INT, HOST_WIDE_INT);
static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
-static void report_architecture_mismatch (void);
static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3701,6 +3700,7 @@ rs6000_option_override_internal (bool global_init_p)
bool ret = true;
HOST_WIDE_INT set_masks;
+ HOST_WIDE_INT ignore_masks;
int cpu_index = -1;
int tune_index;
struct cl_target_option *main_target_opt
@@ -3969,13 +3969,59 @@ rs6000_option_override_internal (bool global_init_p)
dwarf_offset_size = POINTER_SIZE_UNITS;
#endif
- /* Report trying to use things like -mmodulo to imply -mcpu=power9. */
- report_architecture_mismatch ();
+ /* Handle explicit -mno-{altivec,vsx} and turn off all of
+ the options that depend on those flags. */
+ ignore_masks = rs6000_disable_incompatible_switches ();
+
+ /* For the newer switches (vsx, dfp, etc.) set some of the older options,
+ unless the user explicitly used the -mno-<option> to disable the code. */
+ if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
+ rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_P9_MINMAX)
+ {
+ if (cpu_index >= 0)
+ {
+ if (cpu_index == PROCESSOR_POWER9)
+ {
+ /* legacy behavior: allow -mcpu=power9 with certain
+ capabilities explicitly disabled. */
+ rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
+ }
+ else
+ error ("power9 target option is incompatible with %<%s=<xxx>%> "
+ "for <xxx> less than power9", "-mcpu");
+ }
+ else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
+ != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
+ & rs6000_isa_flags_explicit))
+ /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
+ were explicitly cleared. */
+ error ("%qs incompatible with explicitly disabled options",
+ "-mpower9-minmax");
+ else
+ rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
+ }
+ else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
+ rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_VSX)
+ rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_POWER7)
+ rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
+ else if (TARGET_DFP)
+ rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
+ else if (TARGET_POWER6)
+ rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
+ else if (TARGET_POWER5X)
+ rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
+ else if (TARGET_POWER5)
+ rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
+ else if (TARGET_ALTIVEC)
+ rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
/* Disable VSX and Altivec silently if the user switched cpus to power7 in a
target attribute or pragma which automatically enables both options,
unless the altivec ABI was set. This is set by default for 64-bit, but
- not for 32-bit. Don't move this before report_architecture_mismatch
+ not for 32-bit. Don't move this before the above code using ignore_masks,
since it can reset the cleared VSX/ALTIVEC flag again. */
if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
{
@@ -25379,81 +25425,6 @@ rs6000_disable_incompatible_switches (void)
return ignore_masks;
}
-/* In the past, we would boost up the ISA if you selected an -m<foo> option but
- did not specify the correct -mcpu=<bar> option. I.e. if you added -mvsx,
- GCC implictly would assume that you were building for at least power7. Now,
- don't allow the -m<foo> option to boost up the ISA level. But you can still
- do -mcpu=power7 -mno-vsx or -mcpu=power5 -mno-vsx. */
-
-static void
-report_architecture_mismatch (void)
-{
- HOST_WIDE_INT ignore_masks = rs6000_disable_incompatible_switches ();
-
- static const struct {
- const HOST_WIDE_INT isa_flags; /* -m<foo> optiona. */
- const HOST_WIDE_INT arch_flags; /* -mcpu=<proc> level. */
- const char *const arch_name; /* architecture needed. */
- } mismatches[] = {
- {
- OPTION_MASK_P9_VECTOR | OPTION_MASK_P9_MISC | OPTION_MASK_P9_MINMAX
- | OPTION_MASK_MODULO,
- ARCH_MASK_POWER9,
- "-mcpu=power9"
- },
-
- {
- OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO,
- ARCH_MASK_POWER8,
- "-mcpu=power8"
- },
-
- {
- OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
- ARCH_MASK_POWER7,
- "-mcpu=power7"
- },
- };
-
- HOST_WIDE_INT isa_flags = rs6000_isa_flags;
- HOST_WIDE_INT arch_flags = rs6000_arch_flags;
-
- for (size_t i = 0; i < ARRAY_SIZE (mismatches); i++)
- {
- HOST_WIDE_INT mismatch_isa_flags = mismatches[i].isa_flags & isa_flags;
- HOST_WIDE_INT mismatch_arch_flags = mismatches[i].arch_flags &
arch_flags;
-
- if (mismatch_isa_flags != 0 && mismatch_arch_flags == 0)
- {
- for (size_t j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
- {
- HOST_WIDE_INT mask = rs6000_opt_masks[j].mask;
-
- if ((mask & mismatch_isa_flags) != 0
- && (mask & rs6000_isa_flags_explicit) != 0)
- error ("%qs needs at least %qs",
- rs6000_opt_masks[j].name,
- mismatches[i].arch_name);
- }
-
- rs6000_isa_flags &= ~mismatch_isa_flags;
- }
- }
-
- /* The following old options are used in multiple processors, so silently
- enable the appropriate ISA options as previous GCC revisions did. */
- if (TARGET_DFP)
- rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_CMPB)
- rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
- else if (TARGET_POWER5X)
- rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
- else if (TARGET_POPCNTB)
- rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
- else if (TARGET_ALTIVEC)
- rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
-}
-
/* Helper function for printing the function name when debugging. */
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index 5e2ecf34f249..feef76db4618 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_fprs } */
/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
+/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
/* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
/* { dg-final { scan-assembler-times "fadds" 1 } } */
@@ -18,6 +18,10 @@
#error "__VSX__ should not be defined."
#endif
+#pragma GCC target("altivec,vsx")
+#include <altivec.h>
+#pragma GCC reset_options
+
#pragma GCC push_options
#pragma GCC target("altivec,no-vsx")
@@ -29,7 +33,6 @@
#error "__VSX__ should not be defined."
#endif
-/* Altivec build, generate vaddfp. */
void
av_add (vector float *a, vector float *b, vector float *c)
{
@@ -37,11 +40,10 @@ av_add (vector float *a, vector float *b, vector float *c)
unsigned long n = SIZE / 4;
for (i = 0; i < n; i++)
- a[i] = b[i] + c[i];
+ a[i] = vec_add (b[i], c[i]);
}
-/* cpu=power7 must be used to enable VSX. */
-#pragma GCC target("cpu=power7,vsx")
+#pragma GCC target("vsx")
#ifndef __ALTIVEC__
#error "__ALTIVEC__ should be defined."
@@ -51,7 +53,6 @@ av_add (vector float *a, vector float *b, vector float *c)
#error "__VSX__ should be defined."
#endif
-/* VSX build on power7, generate xsaddsp. */
void
vsx_add (vector float *a, vector float *b, vector float *c)
{
@@ -59,31 +60,11 @@ vsx_add (vector float *a, vector float *b, vector float *c)
unsigned long n = SIZE / 4;
for (i = 0; i < n; i++)
- a[i] = b[i] + c[i];
-}
-
-#pragma GCC target("cpu=power7,no-vsx")
-
-#ifndef __ALTIVEC__
-#error "__ALTIVEC__ should be defined."
-#endif
-
-#ifdef __VSX__
-#error "__VSX__ should not be defined."
-#endif
-
-/* Altivec build on power7 with no VSX, generate vaddfp. */
-void
-av2_add (vector float *a, vector float *b, vector float *c)
-{
- unsigned long i;
- unsigned long n = SIZE / 4;
-
- for (i = 0; i < n; i++)
- a[i] = b[i] + c[i];
+ a[i] = vec_add (b[i], c[i]);
}
#pragma GCC pop_options
+#pragma GCC target("no-vsx,no-altivec")
#ifdef __ALTIVEC__
#error "__ALTIVEC__ should not be defined."
@@ -93,7 +74,6 @@ av2_add (vector float *a, vector float *b, vector float *c)
#error "__VSX__ should not be defined."
#endif
-/* Default power5 build, generate scalar fadds. */
void
norm_add (float *a, float *b, float *c)
{
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 00c7c301436a..5222e66ef170 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,8 +7,7 @@
/* Verify there is no ICE under 32 bit env. */
-/* cpu=power7 must be used to enable VSX. */
-__attribute__((target("cpu=power7,vsx")))
+__attribute__((target("vsx")))
int test (void)
{
return 0;
