https://gcc.gnu.org/g:1ae84f1acfbb9a2e3f8f548e2b7c65f482f0901c
commit 1ae84f1acfbb9a2e3f8f548e2b7c65f482f0901c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri Nov 15 09:40:38 2024 -0500
Revert changes
Diff:
---
gcc/config/rs6000/dfp.md | 2 +-
gcc/config/rs6000/rs6000-builtin.cc | 14 +++----
gcc/config/rs6000/rs6000-string.cc | 2 +-
gcc/config/rs6000/rs6000.cc | 34 ++++++++---------
gcc/config/rs6000/rs6000.h | 47 ++++++++++-------------
gcc/config/rs6000/rs6000.md | 76 ++++++++++++++++++-------------------
6 files changed, 84 insertions(+), 91 deletions(-)
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index b8189390d410..fa9d7dd45dd3 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POWER7"
+ "TARGET_DFP && TARGET_POPCNTD"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index b6093b3cb64c..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,23 +155,23 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_ALWAYS:
return true;
case ENB_P5:
- return TARGET_POWER5;
+ return TARGET_POPCNTB;
case ENB_P6:
- return TARGET_POWER6;
+ return TARGET_CMPB;
case ENB_P6_64:
- return TARGET_POWER6 && TARGET_POWERPC64;
+ return TARGET_CMPB && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POWER7;
+ return TARGET_POPCNTD;
case ENB_P7_64:
- return TARGET_POWER7 && TARGET_POWERPC64;
+ return TARGET_POPCNTD && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
return TARGET_P8_VECTOR;
case ENB_P9:
- return TARGET_POWER9;
+ return TARGET_MODULO;
case ENB_P9_64:
- return TARGET_POWER9 && TARGET_POWERPC64;
+ return TARGET_MODULO && TARGET_POWERPC64;
case ENB_P9V:
return TARGET_P9_VECTOR;
case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index b633d80110d0..de618da9b5dc 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
expand_block_compare (rtx operands[])
{
/* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POWER7);
+ gcc_assert (TARGET_POPCNTD);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6b58c060f539..950fd947fda3 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1922,7 +1922,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POWER7 && mode == SImode)
+ if (TARGET_POPCNTD && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -3886,7 +3886,7 @@ rs6000_option_override_internal (bool global_init_p)
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
- if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
+ if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
else if (TARGET_P9_MINMAX)
{
@@ -3916,15 +3916,15 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POWER7)
+ else if (TARGET_POPCNTD)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POWER6)
+ else if (TARGET_CMPB)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
- else if (TARGET_POWER5X)
+ else if (TARGET_FPRND)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
- else if (TARGET_POWER5)
+ else if (TARGET_POPCNTB)
rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
else if (TARGET_ALTIVEC)
rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
@@ -3949,7 +3949,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
}
- if (!TARGET_POWER5X && TARGET_VSX)
+ if (!TARGET_FPRND && TARGET_VSX)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
/* TARGET_VSX = 1 implies Power 7 and newer */
@@ -4129,7 +4129,7 @@ rs6000_option_override_internal (bool global_init_p)
else if (TARGET_LONG_DOUBLE_128)
{
if (global_options.x_rs6000_ieeequad
- && (!TARGET_POWER7 || !TARGET_VSX))
+ && (!TARGET_POPCNTD || !TARGET_VSX))
error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT)
@@ -4796,7 +4796,7 @@ rs6000_option_override_internal (bool global_init_p)
DERAT mispredict penalty. However the LVE and STVE altivec instructions
need indexed accesses and the type used is the scalar type of the element
being loaded or stored. */
- TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
+ TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
&& !TARGET_ALTIVEC);
/* Set the -mrecip options. */
@@ -22416,7 +22416,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
*total = rs6000_cost->divsi;
}
/* Add in shift and subtract for MOD unless we have a mod instruction. */
- if ((!TARGET_POWER9
+ if ((!TARGET_MODULO
|| (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
&& (code == MOD || code == UMOD))
*total += COSTS_N_INSNS (2);
@@ -22431,11 +22431,11 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case POPCOUNT:
- *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6);
+ *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
return false;
case PARITY:
- *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
+ *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
return false;
case NOT:
@@ -23208,8 +23208,8 @@ rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
return;
}
-/* Emit popcount intrinsic on TARGET_POWER5 and TARGET_POWER7 targets. DST is
- the target, and SRC is the argument operand. */
+/* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
+ (Power7) targets. DST is the target, and SRC is the argument operand. */
void
rs6000_emit_popcount (rtx dst, rtx src)
@@ -23218,7 +23218,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
rtx tmp1, tmp2;
/* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
- if (TARGET_POWER7)
+ if (TARGET_POPCNTD)
{
if (mode == SImode)
emit_insn (gen_popcntdsi2 (dst, src));
@@ -23250,7 +23250,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
}
-/* Emit parity intrinsic on TARGET_POWER5 targets. DST is the
+/* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
target, and SRC is the argument operand. */
void
@@ -23262,7 +23262,7 @@ rs6000_emit_parity (rtx dst, rtx src)
tmp = gen_reg_rtx (mode);
/* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
- if (TARGET_POWER6)
+ if (TARGET_CMPB)
{
if (mode == SImode)
{
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3d55e078df0b..d460eb065448 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -442,30 +442,30 @@ extern int rs6000_vector_align[];
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
#define TARGET_IEEEQUAD rs6000_ieeequad
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
-#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL)
+#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POWER7) /* ISA 2.06 */
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_POWER6
-#define TARGET_LFIWZX TARGET_POWER7
-#define TARGET_FCFIDS TARGET_POWER7
-#define TARGET_FCFIDU TARGET_POWER7
-#define TARGET_FCFIDUS TARGET_POWER7
-#define TARGET_FCTIDUZ TARGET_POWER7
-#define TARGET_FCTIWUZ TARGET_POWER7
+#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWZX TARGET_POPCNTD
+#define TARGET_FCFIDS TARGET_POPCNTD
+#define TARGET_FCFIDU TARGET_POPCNTD
+#define TARGET_FCFIDUS TARGET_POPCNTD
+#define TARGET_FCTIDUZ TARGET_POPCNTD
+#define TARGET_FCTIWUZ TARGET_POPCNTD
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_POWER9
-#define TARGET_EXTSWSLI (TARGET_POWER9 && TARGET_POWERPC64)
-#define TARGET_MADDLD TARGET_POWER9
+#define TARGET_CTZ TARGET_MODULO
+#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
+#define TARGET_MADDLD TARGET_MODULO
/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.
*/
#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -501,13 +501,6 @@ extern int rs6000_vector_align[];
#define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
&& (TARGET_P9_MINMAX || !flag_trapping_math))
-/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */
-#define TARGET_POWER5 TARGET_POPCNTB
-#define TARGET_POWER5X TARGET_FPRND
-#define TARGET_POWER6 TARGET_CMPB
-#define TARGET_POWER7 TARGET_POPCNTD
-#define TARGET_POWER9 TARGET_MODULO
-
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx>
options that have not yet been replaced by their OPTION_MASK_<xxx>
@@ -534,9 +527,9 @@ extern int rs6000_vector_align[];
#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POWER7 /* ISA 2.06 */ \
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
|| TARGET_HARD_FLOAT)
@@ -550,9 +543,9 @@ extern int rs6000_vector_align[];
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
#define TARGET_FRE (TARGET_HARD_FLOAT \
- && (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
+ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
-#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POWER5 \
+#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
&& TARGET_PPC_GFXOPT)
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
@@ -1745,7 +1738,7 @@ typedef struct rs6000_args
zero. The hardware instructions added in Power9 and the sequences using
popcount return 32 or 64. */
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
- (TARGET_CTZ || TARGET_POWER7 \
+ (TARGET_CTZ || TARGET_POPCNTD
\
? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
: ((VALUE) = -1, 2))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bb83e30311e5..8eda2f7bb0d7 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -379,15 +379,15 @@
(const_int 1)
(and (eq_attr "isa" "p5")
- (match_test "TARGET_POWER5"))
+ (match_test "TARGET_POPCNTB"))
(const_int 1)
(and (eq_attr "isa" "p6")
- (match_test "TARGET_POWER6"))
+ (match_test "TARGET_CMPB"))
(const_int 1)
(and (eq_attr "isa" "p7")
- (match_test "TARGET_POWER7"))
+ (match_test "TARGET_POPCNTD"))
(const_int 1)
(and (eq_attr "isa" "p7v")
@@ -403,7 +403,7 @@
(const_int 1)
(and (eq_attr "isa" "p9")
- (match_test "TARGET_POWER9"))
+ (match_test "TARGET_MODULO"))
(const_int 1)
(and (eq_attr "isa" "p9v")
@@ -2466,7 +2466,7 @@
rtx tmp2 = gen_reg_rtx (<MODE>mode);
rtx tmp3 = gen_reg_rtx (<MODE>mode);
- if (TARGET_POWER7)
+ if (TARGET_POPCNTD)
{
emit_insn (gen_add<mode>3 (tmp1, operands[1], constm1_rtx));
emit_insn (gen_one_cmpl<mode>2 (tmp2, operands[1]));
@@ -2510,7 +2510,7 @@
(define_expand "popcount<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB || TARGET_POPCNTD"
{
rs6000_emit_popcount (operands[0], operands[1]);
DONE;
@@ -2520,14 +2520,14 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_POPCNTB))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB"
"popcntb %0,%1"
[(set_attr "type" "popcnt")])
(define_insn "popcntd<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"popcnt<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2535,7 +2535,7 @@
(define_expand "parity<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB"
{
rs6000_emit_parity (operands[0], operands[1]);
DONE;
@@ -2544,7 +2544,7 @@
(define_insn "parity<mode>2_cmpb"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_PARITY))]
- "TARGET_POWER6"
+ "TARGET_CMPB && TARGET_POPCNTB"
"prty<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2597,7 +2597,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
- "TARGET_POWER6"
+ "TARGET_CMPB"
"cmpb %0,%1,%2"
[(set_attr "type" "cmp")])
@@ -3457,7 +3457,7 @@
|| INTVAL (operands[2]) <= 0
|| (i = exact_log2 (INTVAL (operands[2]))) < 0)
{
- if (!TARGET_POWER9)
+ if (!TARGET_MODULO)
FAIL;
operands[2] = force_reg (<MODE>mode, operands[2]);
@@ -3491,7 +3491,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
(mod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
(match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
- "TARGET_POWER9 && !RS6000_DISABLE_SCALAR_MODULO"
+ "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
"mods<wd> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
@@ -3502,7 +3502,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand")
(umod:GPR (match_operand:GPR 1 "gpc_reg_operand")
(match_operand:GPR 2 "gpc_reg_operand")))]
- "TARGET_POWER9"
+ "TARGET_MODULO"
{
if (RS6000_DISABLE_SCALAR_MODULO)
{
@@ -3520,7 +3520,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
(umod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
(match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
- "TARGET_POWER9 && !RS6000_DISABLE_SCALAR_MODULO"
+ "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
"modu<wd> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
@@ -3536,7 +3536,7 @@
(set (match_operand:GPR 3 "gpc_reg_operand")
(mod:GPR (match_dup 1)
(match_dup 2)))]
- "TARGET_POWER9
+ "TARGET_MODULO
&& ! reg_mentioned_p (operands[0], operands[1])
&& ! reg_mentioned_p (operands[0], operands[2])
&& ! reg_mentioned_p (operands[3], operands[1])
@@ -3558,7 +3558,7 @@
(set (match_operand:GPR 3 "gpc_reg_operand")
(umod:GPR (match_dup 1)
(match_dup 2)))]
- "TARGET_POWER9
+ "TARGET_MODULO
&& ! reg_mentioned_p (operands[0], operands[1])
&& ! reg_mentioned_p (operands[0], operands[2])
&& ! reg_mentioned_p (operands[3], operands[1])
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_POWER5X
+ && TARGET_FPRND
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_POWER5X
+ && TARGET_FPRND
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -5401,7 +5401,7 @@
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
- || TARGET_POWER6
+ || TARGET_CMPB
|| VECTOR_UNIT_VSX_P (<MODE>mode))"
{
/* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5422,7 +5422,7 @@
if (!gpc_reg_operand (operands[2], <MODE>mode))
operands[2] = copy_to_mode_reg (<MODE>mode, operands[2]);
- if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))
+ if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
{
emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
operands[2]));
@@ -5438,7 +5438,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
- "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
@@ -6687,7 +6687,7 @@
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X
+ "TARGET_HARD_FLOAT && TARGET_FPRND
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@@ -6784,7 +6784,7 @@
/* For those old archs in which SImode can't be hold in float registers,
call lrint<mode>si_di to put the result in DImode then convert it via
stack. */
- if (!TARGET_POWER7)
+ if (!TARGET_POPCNTD)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_lrint<mode>si_di (tmp, operands[1]));
@@ -6799,7 +6799,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=d")
(unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && TARGET_POWER7"
+ "TARGET_HARD_FLOAT && TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6807,7 +6807,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && !TARGET_POWER7"
+ "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6815,7 +6815,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIZ))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIP))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIM))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FRIN))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"frin %0,%1"
[(set_attr "type" "fp")])
@@ -10122,7 +10122,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10144,7 +10144,7 @@
(compare:SI (match_operand:BLK 1)
(match_operand:BLK 2)))
(use (match_operand:SI 3))])]
- "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10168,7 +10168,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -14435,7 +14435,7 @@
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"bpermd %0,%1,%2"
[(set_attr "type" "popcnt")])
@@ -14813,7 +14813,7 @@
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")]
UNSPEC_ADDG6S))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"addg6s %0,%1,%2"
[(set_attr "type" "integer")])
@@ -14821,7 +14821,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CDTBCD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cdtbcd %0,%1"
[(set_attr "type" "integer")])
@@ -14829,7 +14829,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CBCDTD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cbcdtd %0,%1"
[(set_attr "type" "integer")])
@@ -14844,7 +14844,7 @@
(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
(match_operand:GPR 2 "register_operand" "r")]
UNSPEC_DIV_EXTEND))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"div<wd><div_extend> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
