https://gcc.gnu.org/g:d553483426809f56c5a3fa80d598bc5549a9d74a
commit d553483426809f56c5a3fa80d598bc5549a9d74a
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Nov 14 21:37:18 2024 -0500
Revert changes
Diff:
---
gcc/config/rs6000/default64.h | 11 --
gcc/config/rs6000/dfp.md | 2 +-
gcc/config/rs6000/rs6000-arch.def | 48 -------
gcc/config/rs6000/rs6000-builtin.cc | 14 +-
gcc/config/rs6000/rs6000-c.cc | 10 +-
gcc/config/rs6000/rs6000-cpus.def | 46 +++----
gcc/config/rs6000/rs6000-string.cc | 2 +-
gcc/config/rs6000/rs6000.cc | 263 ++++++++----------------------------
gcc/config/rs6000/rs6000.h | 64 +++------
gcc/config/rs6000/rs6000.md | 76 +++++------
gcc/config/rs6000/rs6000.opt | 38 ++----
11 files changed, 165 insertions(+), 409 deletions(-)
diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
index afa6542e040c..10e3dec78aca 100644
--- a/gcc/config/rs6000/default64.h
+++ b/gcc/config/rs6000/default64.h
@@ -21,7 +21,6 @@ along with GCC; see the file COPYING3. If not see
#define RS6000_CPU(NAME, CPU, FLAGS)
#include "rs6000-cpus.def"
#undef RS6000_CPU
-#undef TARGET_CPU_DEFAULT
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#undef TARGET_DEFAULT
@@ -29,20 +28,10 @@ along with GCC; see the file COPYING3. If not see
| MASK_LITTLE_ENDIAN)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpower8"
-#define TARGET_CPU_DEFAULT "power8"
-
#else
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \
| OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mpower4"
-
-#if (TARGET_DEFAULT & MASK_POWERPC64)
-#define TARGET_CPU_DEFAULT "powerpc64"
-
-#else
-#define TARGET_CPU_DEFAULT "powerpc"
-#endif
-
#endif
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index b8189390d410..fa9d7dd45dd3 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
- "TARGET_DFP && TARGET_POWER7"
+ "TARGET_DFP && TARGET_POPCNTD"
"dcffix %0,%1"
[(set_attr "type" "dfp")])
diff --git a/gcc/config/rs6000/rs6000-arch.def
b/gcc/config/rs6000/rs6000-arch.def
deleted file mode 100644
index e5b6e9581331..000000000000
--- a/gcc/config/rs6000/rs6000-arch.def
+++ /dev/null
@@ -1,48 +0,0 @@
-/* IBM RS/6000 CPU architecture features by processor type.
- Copyright (C) 1991-2024 Free Software Foundation, Inc.
- Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-/* This file defines architecture features that are based on the -mcpu=<proc>
- option, and not on user options that can be turned on or off. The intention
- is for newer processors (power7 and above) to not add new ISA bits for the
- particular processor, but add these bits. Otherwise we have to add a bunch
- of hidden options, just so we have the proper ISA bits.
-
- For example, in the past we added -mpower8-internal, so that on power8,
- power9, and power10 would inherit the option, but we had to mark the option
- generate a warning if the user actually used it. These options have been
- moved from the ISA flags to the arch flags.
-
- To use this, define the macro ARCH_EXPAND which takes 2 arguments. The
- first argument is the processor name in upper case, and the second argument
- is a text name for the processor.
-
- The function get_arch_flags when passed a processor index number will set up
- the appropriate architecture flags based on the actual processor
- enumeration. */
-
-ARCH_EXPAND(POWER4, "power4")
-ARCH_EXPAND(POWER5, "power5")
-ARCH_EXPAND(POWER5X, "power5+")
-ARCH_EXPAND(POWER6, "power6")
-ARCH_EXPAND(POWER7, "power7")
-ARCH_EXPAND(POWER8, "power8")
-ARCH_EXPAND(POWER9, "power9")
-ARCH_EXPAND(POWER10, "power10")
-ARCH_EXPAND(POWER11, "power11")
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index b6093b3cb64c..9bdbae1ecf94 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,23 +155,23 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_ALWAYS:
return true;
case ENB_P5:
- return TARGET_POWER5;
+ return TARGET_POPCNTB;
case ENB_P6:
- return TARGET_POWER6;
+ return TARGET_CMPB;
case ENB_P6_64:
- return TARGET_POWER6 && TARGET_POWERPC64;
+ return TARGET_CMPB && TARGET_POWERPC64;
case ENB_P7:
- return TARGET_POWER7;
+ return TARGET_POPCNTD;
case ENB_P7_64:
- return TARGET_POWER7 && TARGET_POWERPC64;
+ return TARGET_POPCNTD && TARGET_POWERPC64;
case ENB_P8:
return TARGET_POWER8;
case ENB_P8V:
return TARGET_P8_VECTOR;
case ENB_P9:
- return TARGET_POWER9;
+ return TARGET_MODULO;
case ENB_P9_64:
- return TARGET_POWER9 && TARGET_POWERPC64;
+ return TARGET_MODULO && TARGET_POWERPC64;
case ENB_P9V:
return TARGET_P9_VECTOR;
case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 25c662a9ca86..4dc80e598fa4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -422,17 +422,17 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
if ((flags & OPTION_MASK_MFCRF) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
- if ((flags & OPTION_MASK_POWER5) != 0)
+ if ((flags & OPTION_MASK_POPCNTB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
- if ((flags & OPTION_MASK_POWER5X) != 0)
+ if ((flags & OPTION_MASK_FPRND) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
- if ((flags & OPTION_MASK_POWER6) != 0)
+ if ((flags & OPTION_MASK_CMPB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
- if ((flags & OPTION_MASK_POWER7) != 0)
+ if ((flags & OPTION_MASK_POPCNTD) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
if ((flags & OPTION_MASK_POWER8) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
- if ((flags & OPTION_MASK_POWER9) != 0)
+ if ((flags & OPTION_MASK_MODULO) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
if ((flags & OPTION_MASK_POWER10) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index c84af0c54cae..84fac8bdac1d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -21,14 +21,14 @@
/* ISA masks. */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS OPTION_MASK_MFCRF
-#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POWER5)
-#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_POWER5X)
+#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
/* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
as optional. Group masks by server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
- | OPTION_MASK_POWER6 \
+ | OPTION_MASK_CMPB \
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT)
@@ -37,9 +37,9 @@
/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
altivec is a win so enable it. */
-#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POWER7)
+#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
- | OPTION_MASK_POWER7 \
+ | OPTION_MASK_POPCNTD \
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX)
@@ -62,7 +62,7 @@
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
| OPTION_MASK_ISEL \
- | OPTION_MASK_POWER9 \
+ | OPTION_MASK_MODULO \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR) \
@@ -117,14 +117,14 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
- | OPTION_MASK_POWER6 \
+ | OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
| OPTION_MASK_DLMZB \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
- | OPTION_MASK_POWER5X \
+ | OPTION_MASK_FPRND \
| OPTION_MASK_POWER10 \
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
@@ -132,7 +132,7 @@
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MMA \
- | OPTION_MASK_POWER9 \
+ | OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
| OPTION_MASK_POWER8 \
@@ -143,8 +143,8 @@
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_PCREL \
| OPTION_MASK_PCREL_OPT \
- | OPTION_MASK_POWER5 \
- | OPTION_MASK_POWER7 \
+ | OPTION_MASK_POPCNTB \
+ | OPTION_MASK_POPCNTD \
| OPTION_MASK_POWERPC64 \
| OPTION_MASK_PPC_GFXOPT \
| OPTION_MASK_PPC_GPOPT \
@@ -184,12 +184,12 @@ RS6000_CPU ("464", PROCESSOR_PPC440,
OPTION_MASK_SOFT_FLOAT
| OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_POWER5X | OPTION_MASK_POWER6 | OPTION_MASK_MULHW
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
| OPTION_MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
- | OPTION_MASK_MFCRF | OPTION_MASK_POWER5 | OPTION_MASK_POWER5X
- | OPTION_MASK_POWER6 | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
+ | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
+ | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
@@ -209,7 +209,7 @@ RS6000_CPU ("823", PROCESSOR_MPCCORE,
OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64
- | OPTION_MASK_POWER5 | OPTION_MASK_POWER6
+ | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB
| OPTION_MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
@@ -236,17 +236,17 @@ RS6000_CPU ("power3", PROCESSOR_PPC630,
OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
| OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5)
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_POWER5X)
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_POWER5X | OPTION_MASK_POWER6 | OPTION_MASK_DFP
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
- | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POWER5
- | OPTION_MASK_POWER5X | OPTION_MASK_POWER6 | OPTION_MASK_DFP
+ | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
+ | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
| OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index b633d80110d0..de618da9b5dc 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1949,7 +1949,7 @@ bool
expand_block_compare (rtx operands[])
{
/* TARGET_POPCNTD is already guarded at expand cmpmemsi. */
- gcc_assert (TARGET_POWER7);
+ gcc_assert (TARGET_POPCNTD);
/* For P8, this case is complicated to handle because the subtract
with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b658c1f2bcc4..950fd947fda3 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -252,17 +252,17 @@ enum {
/* Map compiler ISA bits into HWCAP names. */
struct clone_map {
- HOST_WIDE_INT arch_mask; /* rs6000_arch mask */
+ HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
const char *name; /* name to use in __builtin_cpu_supports. */
};
static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
- { 0, "" }, /* Default options. */
- { ARCH_MASK_POWER6, "arch_2_05" }, /* ISA 2.5 (power6). */
- { ARCH_MASK_POWER7, "arch_2_06" }, /* ISA 2.6 (power7). */
- { ARCH_MASK_POWER8, "arch_2_07" }, /* ISA 2.7 (power8). */
- { ARCH_MASK_POWER9, "arch_3_00" }, /* ISA 3.0 (power9). */
- { ARCH_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
+ { 0, "" }, /* Default options. */
+ { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
+ { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
+ { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
+ { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.0 (power9). */
+ { OPTION_MASK_POWER10, "arch_3_1" }, /* ISA 3.1 (power10). */
};
@@ -1171,7 +1171,7 @@ enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx,
enum reg_class)
const int INSN_NOT_AVAILABLE = -1;
static void rs6000_print_isa_options (FILE *, int, const char *,
- HOST_WIDE_INT, HOST_WIDE_INT);
+ HOST_WIDE_INT);
static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
@@ -1818,82 +1818,6 @@ rs6000_cpu_name_lookup (const char *name)
return -1;
}
-
-/* Map the processor into the arch bits that are set off of -mcpu=<xxx> instead
- of having an internal -m<foo> option. */
-
-static HOST_WIDE_INT
-get_arch_flags (int cpu_index)
-{
- HOST_WIDE_INT ret = 0;
-
- const HOST_WIDE_INT ARCH_COMBO_POWER4 = ARCH_MASK_POWER4;
- const HOST_WIDE_INT ARCH_COMBO_POWER5 = ARCH_MASK_POWER5 |
ARCH_COMBO_POWER4;
- const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X |
ARCH_COMBO_POWER5;
- const HOST_WIDE_INT ARCH_COMBO_POWER6 = ARCH_MASK_POWER6 |
ARCH_COMBO_POWER5X;
- const HOST_WIDE_INT ARCH_COMBO_POWER7 = ARCH_MASK_POWER7 |
ARCH_COMBO_POWER6;
- const HOST_WIDE_INT ARCH_COMBO_POWER8 = ARCH_MASK_POWER8 |
ARCH_COMBO_POWER7;
- const HOST_WIDE_INT ARCH_COMBO_POWER9 = ARCH_MASK_POWER9 |
ARCH_COMBO_POWER8;
- const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 |
ARCH_COMBO_POWER9;
- const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 |
ARCH_COMBO_POWER10;
-
- if (cpu_index >= 0)
- switch (processor_target_table[cpu_index].processor)
- {
- case PROCESSOR_POWER11:
- ret = ARCH_COMBO_POWER11;
- break;
-
- case PROCESSOR_POWER10:
- ret = ARCH_COMBO_POWER10;
- break;
-
- case PROCESSOR_POWER9:
- ret = ARCH_COMBO_POWER9;
- break;
-
- case PROCESSOR_POWER8:
- ret = ARCH_COMBO_POWER8;
- break;
-
- case PROCESSOR_POWER7:
- ret = ARCH_COMBO_POWER7;
- break;
-
- case PROCESSOR_PPCA2:
- case PROCESSOR_POWER6:
- ret = ARCH_COMBO_POWER6;
- break;
-
- case PROCESSOR_POWER5:
- ret = ARCH_COMBO_POWER5;
- if (TARGET_POWER5X)
- ret |= ARCH_MASK_POWER5X;
- break;
-
- case PROCESSOR_POWER4:
- ret = ARCH_COMBO_POWER4;
- break;
-
- default:
- /* For other processors, set the arch flags based on the ISA bits. */
- if (TARGET_MFCRF)
- ret |= ARCH_MASK_POWER4;
-
- if (TARGET_POWER5)
- ret |= ARCH_MASK_POWER5;
-
- if (TARGET_POWER5X)
- ret |= ARCH_MASK_POWER5X;
-
- if (TARGET_POWER6)
- ret |= ARCH_MASK_POWER6;
- break;
- }
-
- return ret;
-}
-
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
@@ -1998,7 +1922,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_POWER7 && mode == SImode)
+ if (TARGET_POPCNTD && mode == SImode)
return 1;
if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -2475,10 +2399,9 @@ rs6000_debug_reg_global (void)
const char *name = processor_target_table[rs6000_cpu_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_cpu_index].target_enable;
- HOST_WIDE_INT arch_flags = get_arch_flags (rs6000_cpu_index);
sprintf (flags_buffer, "-mcpu=%s flags", name);
- rs6000_print_isa_options (stderr, 0, flags_buffer, flags, arch_flags);
+ rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
@@ -2488,26 +2411,21 @@ rs6000_debug_reg_global (void)
const char *name = processor_target_table[rs6000_tune_index].name;
HOST_WIDE_INT flags
= processor_target_table[rs6000_tune_index].target_enable;
- HOST_WIDE_INT arch_flags = get_arch_flags (rs6000_tune_index);
sprintf (flags_buffer, "-mtune=%s flags", name);
- rs6000_print_isa_options (stderr, 0, flags_buffer, flags, arch_flags);
+ rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
}
else
fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
cl_target_option_save (&cl_opts, &global_options, &global_options_set);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
- rs6000_isa_flags, 0);
+ rs6000_isa_flags);
rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
- rs6000_isa_flags_explicit, 0);
-
- if (rs6000_arch_flags)
- rs6000_print_isa_options (stderr, 0, "rs6000_arch_flags", 0,
- rs6000_arch_flags);
+ rs6000_isa_flags_explicit);
- rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT, 0);
+ rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
@@ -3704,7 +3622,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Print defaults. */
if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
- rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT, 0);
+ rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
/* Remember the explicit arguments. */
if (global_init_p)
@@ -3835,8 +3753,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
}
- rs6000_arch_flags = get_arch_flags (cpu_index);
-
/* Don't expect powerpc64 enabled on those OSes with OS_MISSING_POWERPC64,
since they do not save and restore the high half of the GPRs correctly
in all cases. If the user explicitly specifies it, we won't interfere
@@ -3956,8 +3872,7 @@ rs6000_option_override_internal (bool global_init_p)
& ~rs6000_isa_flags_explicit);
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
#ifdef XCOFF_DEBUGGING_INFO
/* For AIX default to 64-bit DWARF. */
@@ -3971,7 +3886,7 @@ rs6000_option_override_internal (bool global_init_p)
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
- if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
+ if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
else if (TARGET_P9_MINMAX)
{
@@ -4001,15 +3916,15 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
else if (TARGET_VSX)
rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POWER7)
+ else if (TARGET_POPCNTD)
rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
else if (TARGET_DFP)
rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
- else if (TARGET_POWER6)
+ else if (TARGET_CMPB)
rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
- else if (TARGET_POWER5X)
+ else if (TARGET_FPRND)
rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
- else if (TARGET_POWER5)
+ else if (TARGET_POPCNTB)
rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
else if (TARGET_ALTIVEC)
rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
@@ -4034,12 +3949,12 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
}
- if (!TARGET_POWER5X && TARGET_VSX)
+ if (!TARGET_FPRND && TARGET_VSX)
{
- if (rs6000_isa_flags_explicit & OPTION_MASK_POWER5X)
+ if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
/* TARGET_VSX = 1 implies Power 7 and newer */
error ("%qs requires %qs", "-mvsx", "-mfprnd");
- rs6000_isa_flags &= ~OPTION_MASK_POWER5X;
+ rs6000_isa_flags &= ~OPTION_MASK_FPRND;
}
/* Assert !TARGET_VSX if !TARGET_ALTIVEC and make some adjustments
@@ -4214,7 +4129,7 @@ rs6000_option_override_internal (bool global_init_p)
else if (TARGET_LONG_DOUBLE_128)
{
if (global_options.x_rs6000_ieeequad
- && (!TARGET_POWER7 || !TARGET_VSX))
+ && (!TARGET_POPCNTD || !TARGET_VSX))
error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT)
@@ -4319,8 +4234,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Print the options after updating the defaults. */
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
/* E500mc does "better" if we inline more aggressively. Respect the
user's opinion, though. */
@@ -4427,8 +4341,7 @@ rs6000_option_override_internal (bool global_init_p)
TARGET_NO_FP_IN_TOC = 1;
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
#ifdef SUBTARGET_OVERRIDE_OPTIONS
SUBTARGET_OVERRIDE_OPTIONS;
@@ -4495,8 +4408,7 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
- rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags,
- rs6000_arch_flags);
+ rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
&& rs6000_tune != PROCESSOR_POWER5
@@ -4884,7 +4796,7 @@ rs6000_option_override_internal (bool global_init_p)
DERAT mispredict penalty. However the LVE and STVE altivec instructions
need indexed accesses and the type used is the scalar type of the element
being loaded or stored. */
- TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_POWER6
+ TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
&& !TARGET_ALTIVEC);
/* Set the -mrecip options. */
@@ -5987,28 +5899,27 @@ rs6000_machine_from_flags (void)
return "ppc64";
#endif
- HOST_WIDE_INT arch_flags = rs6000_arch_flags;
HOST_WIDE_INT flags = rs6000_isa_flags;
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
| OPTION_MASK_ALTIVEC);
- if ((arch_flags & ARCH_MASK_POWER11) != 0)
+ if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
return "power11";
- if ((arch_flags & ARCH_MASK_POWER10) != 0)
+ if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
return "power10";
- if ((arch_flags & ARCH_MASK_POWER9) != 0)
+ if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
return "power9";
- if ((arch_flags & ARCH_MASK_POWER8) != 0)
+ if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
return "power8";
- if ((arch_flags & ARCH_MASK_POWER7) != 0)
+ if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
return "power7";
- if ((arch_flags & ARCH_MASK_POWER6) != 0)
+ if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
return "power6";
- if ((arch_flags & ARCH_MASK_POWER5) != 0)
+ if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
return "power5";
- if ((arch_flags & ARCH_MASK_POWER4) != 0)
+ if ((flags & ISA_2_1_MASKS) != 0)
return "power4";
if ((flags & OPTION_MASK_POWERPC64) != 0)
return "ppc64";
@@ -22505,7 +22416,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
*total = rs6000_cost->divsi;
}
/* Add in shift and subtract for MOD unless we have a mod instruction. */
- if ((!TARGET_POWER9
+ if ((!TARGET_MODULO
|| (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
&& (code == MOD || code == UMOD))
*total += COSTS_N_INSNS (2);
@@ -22520,11 +22431,11 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int
outer_code,
return false;
case POPCOUNT:
- *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6);
+ *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
return false;
case PARITY:
- *total = COSTS_N_INSNS (TARGET_POWER6 ? 2 : 6);
+ *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
return false;
case NOT:
@@ -23297,8 +23208,8 @@ rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
return;
}
-/* Emit popcount intrinsic on TARGET_POWER5 and TARGET_POWER7 targets. DST is
- the target, and SRC is the argument operand. */
+/* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
+ (Power7) targets. DST is the target, and SRC is the argument operand. */
void
rs6000_emit_popcount (rtx dst, rtx src)
@@ -23307,7 +23218,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
rtx tmp1, tmp2;
/* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
- if (TARGET_POWER7)
+ if (TARGET_POPCNTD)
{
if (mode == SImode)
emit_insn (gen_popcntdsi2 (dst, src));
@@ -23339,7 +23250,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
}
-/* Emit parity intrinsic on TARGET_POWER5 targets. DST is the
+/* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
target, and SRC is the argument operand. */
void
@@ -23351,7 +23262,7 @@ rs6000_emit_parity (rtx dst, rtx src)
tmp = gen_reg_rtx (mode);
/* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
- if (TARGET_POWER6)
+ if (TARGET_CMPB)
{
if (mode == SImode)
{
@@ -24571,7 +24482,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
false, true },
{ "block-ops-vector-pair", OPTION_MASK_BLOCK_OPS_VECTOR_PAIR,
false, true },
- { "cmpb", OPTION_MASK_POWER6, false, true },
+ { "cmpb", OPTION_MASK_CMPB, false, true },
{ "crypto", OPTION_MASK_CRYPTO, false, true },
{ "direct-move", 0, false, true },
{ "dlmzb", OPTION_MASK_DLMZB, false, true },
@@ -24579,7 +24490,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
false, true },
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
- { "fprnd", OPTION_MASK_POWER5X, false, true },
+ { "fprnd", OPTION_MASK_FPRND, false, true },
{ "power10", OPTION_MASK_POWER10, false, true },
{ "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
@@ -24588,13 +24499,13 @@ static struct rs6000_opt_mask const
rs6000_opt_masks[] =
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
- { "modulo", OPTION_MASK_POWER9, false, true },
+ { "modulo", OPTION_MASK_MODULO, false, true },
{ "mulhw", OPTION_MASK_MULHW, false, true },
{ "multiple", OPTION_MASK_MULTIPLE, false,
true },
{ "pcrel", OPTION_MASK_PCREL, false, true },
{ "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true },
- { "popcntb", OPTION_MASK_POWER5, false, true },
- { "popcntd", OPTION_MASK_POWER7, false, true },
+ { "popcntb", OPTION_MASK_POPCNTB, false, true },
+ { "popcntd", OPTION_MASK_POPCNTD, false, true },
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
@@ -24638,23 +24549,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[]
=
{ "string", 0, false, false },
};
-/* Similar structure for the arch bits that are set via -mcpu=<xxx> and not via
- a separate -m<yyy> option. */
-struct rs6000_arch_mask {
- const char *name; /* option name */
- const HOST_WIDE_INT mask; /* mask to set */
-};
-
-#undef ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME) { NAME, ARCH_MASK_ ## PROC },
-
-static struct rs6000_arch_mask const rs6000_arch_masks[] =
-{
-#include "rs6000-arch.def"
-};
-
-#undef ARCH_EXPAND
-
/* Option variables that we want to support inside attribute((target)) and
#pragma GCC target operations. */
@@ -25193,7 +25087,6 @@ rs6000_function_specific_save (struct cl_target_option
*ptr,
{
ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
- ptr->x_rs6000_arch_flags = opts->x_rs6000_arch_flags;
}
/* Restore the current options */
@@ -25206,7 +25099,6 @@ rs6000_function_specific_restore (struct gcc_options
*opts,
{
opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
- opts->x_rs6000_arch_flags = ptr->x_rs6000_arch_flags;
(void) rs6000_option_override_internal (false);
}
@@ -25217,12 +25109,10 @@ rs6000_function_specific_print (FILE *file, int
indent,
struct cl_target_option *ptr)
{
rs6000_print_isa_options (file, indent, "Isa options set",
- ptr->x_rs6000_isa_flags,
- ptr->x_rs6000_arch_flags);
+ ptr->x_rs6000_isa_flags);
rs6000_print_isa_options (file, indent, "Isa options explicit",
- ptr->x_rs6000_isa_flags_explicit,
- ptr->x_rs6000_arch_flags);
+ ptr->x_rs6000_isa_flags_explicit);
}
/* Helper function to print the current isa or misc options on a line. */
@@ -25234,18 +25124,13 @@ rs6000_print_options_internal (FILE *file,
HOST_WIDE_INT flags,
const char *prefix,
const struct rs6000_opt_mask *opts,
- size_t num_elements,
- HOST_WIDE_INT arch_flags,
- const char *arch_prefix,
- const struct rs6000_arch_mask *arch_masks,
- size_t num_arch)
+ size_t num_elements)
{
size_t i;
size_t start_column = 0;
size_t cur_column;
size_t max_column = 120;
size_t prefix_len = strlen (prefix);
- size_t arch_prefix_len = strlen (arch_prefix);
size_t comma_len = 0;
const char *comma = "";
@@ -25305,29 +25190,6 @@ rs6000_print_options_internal (FILE *file,
comma_len = strlen (", ");
}
- /* Put out the architecture flag bits that are set via -mcpu=<xxx> and that
- don't have a -m option. */
- for (i = 0; i < num_arch; i++)
- {
- if ((arch_flags & arch_masks[i].mask) != 0)
- {
- const char *name = arch_masks[i].name;
- size_t len = comma_len + arch_prefix_len + strlen (name);
-
- cur_column += len;
- if (cur_column > max_column)
- {
- fprintf (stderr, ", \\\n%*s", (int)start_column, "");
- cur_column = start_column + len;
- comma = "";
- }
-
- fprintf (file, "%s%s%s", comma, arch_prefix, name);
- comma = ", ";
- comma_len = strlen (", ");
- }
- }
-
fputs ("\n", file);
}
@@ -25335,13 +25197,11 @@ rs6000_print_options_internal (FILE *file,
static void
rs6000_print_isa_options (FILE *file, int indent, const char *string,
- HOST_WIDE_INT flags, HOST_WIDE_INT arch_flags)
+ HOST_WIDE_INT flags)
{
rs6000_print_options_internal (file, indent, string, flags, "-m",
&rs6000_opt_masks[0],
- ARRAY_SIZE (rs6000_opt_masks),
- arch_flags, "arch=", &rs6000_arch_masks[0],
- ARRAY_SIZE (rs6000_arch_masks));
+ ARRAY_SIZE (rs6000_opt_masks));
}
/* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
@@ -25431,7 +25291,7 @@ static int
rs6000_clone_priority (tree fndecl)
{
tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
- HOST_WIDE_INT arch_masks;
+ HOST_WIDE_INT isa_masks;
int ret = CLONE_DEFAULT;
tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
const char *attrs_str = NULL;
@@ -25447,12 +25307,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
- arch_masks = rs6000_arch_flags;
+ isa_masks = rs6000_isa_flags;
else
- arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
+ isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
for (ret = CLONE_MAX - 1; ret != 0; ret--)
- if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
+ if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
break;
}
@@ -25932,8 +25792,6 @@ rs6000_can_inline_p (tree caller, tree callee)
HOST_WIDE_INT callee_isa = callee_opts->x_rs6000_isa_flags;
HOST_WIDE_INT caller_isa = caller_opts->x_rs6000_isa_flags;
HOST_WIDE_INT explicit_isa = callee_opts->x_rs6000_isa_flags_explicit;
- HOST_WIDE_INT callee_arch = callee_opts->x_rs6000_arch_flags;
- HOST_WIDE_INT caller_arch = caller_opts->x_rs6000_arch_flags;
cgraph_node *callee_node = cgraph_node::get (callee);
if (ipa_fn_summaries && ipa_fn_summaries->get (callee_node) != NULL)
@@ -25957,8 +25815,7 @@ rs6000_can_inline_p (tree caller, tree callee)
callee has explicitly enabled or disabled, then we must enforce that
the callee's and caller's options match exactly; see PR70010. */
if (((caller_isa & callee_isa) == callee_isa)
- && (caller_isa & explicit_isa) == (callee_isa & explicit_isa)
- && (caller_arch & callee_arch) == callee_arch)
+ && (caller_isa & explicit_isa) == (callee_isa & explicit_isa))
ret = true;
if (TARGET_DEBUG_TARGET)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index e5524f5528f7..d460eb065448 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -442,30 +442,30 @@ extern int rs6000_vector_align[];
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
#define TARGET_IEEEQUAD rs6000_ieeequad
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
-#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL)
+#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POWER7) /* ISA 2.06 */
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_POWER6
-#define TARGET_LFIWZX TARGET_POWER7
-#define TARGET_FCFIDS TARGET_POWER7
-#define TARGET_FCFIDU TARGET_POWER7
-#define TARGET_FCFIDUS TARGET_POWER7
-#define TARGET_FCTIDUZ TARGET_POWER7
-#define TARGET_FCTIWUZ TARGET_POWER7
+#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWZX TARGET_POPCNTD
+#define TARGET_FCFIDS TARGET_POPCNTD
+#define TARGET_FCFIDU TARGET_POPCNTD
+#define TARGET_FCFIDUS TARGET_POPCNTD
+#define TARGET_FCTIDUZ TARGET_POPCNTD
+#define TARGET_FCTIWUZ TARGET_POPCNTD
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_POWER9
-#define TARGET_EXTSWSLI (TARGET_POWER9 && TARGET_POWERPC64)
-#define TARGET_MADDLD TARGET_POWER9
+#define TARGET_CTZ TARGET_MODULO
+#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
+#define TARGET_MADDLD TARGET_MODULO
/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.
*/
#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -527,9 +527,9 @@ extern int rs6000_vector_align[];
#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
- || TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_POWER6 /* ISA 2.05 */ \
- || TARGET_POWER7 /* ISA 2.06 */ \
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
|| TARGET_HARD_FLOAT)
@@ -543,9 +543,9 @@ extern int rs6000_vector_align[];
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
#define TARGET_FRE (TARGET_HARD_FLOAT \
- && (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
+ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
-#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POWER5 \
+#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
&& TARGET_PPC_GFXOPT)
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
@@ -1738,7 +1738,7 @@ typedef struct rs6000_args
zero. The hardware instructions added in Power9 and the sequences using
popcount return 32 or 64. */
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
- (TARGET_CTZ || TARGET_POWER7 \
+ (TARGET_CTZ || TARGET_POPCNTD
\
? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
: ((VALUE) = -1, 2))
@@ -2483,27 +2483,3 @@ while (0)
issues have been resolved. */
#define RS6000_DISABLE_SCALAR_MODULO 1
-
-
-/* Create the architecture flags. */
-/* Define an enumeration to number the architecture masks. */
-#ifdef GCC_HWINT_H
-#undef ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME) ARCH_ENUM_ ## PROC,
-
-enum {
-#include "rs6000-arch.def"
- ARCH_ENUM_LAST
-};
-
-/* Create an architecture mask for the newer architectures (power6 and
- up).. */
-#undef ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)
\
- static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
- = HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
-
-#include "rs6000-arch.def"
-
-#undef ARCH_EXPAND
-#endif /* GCC_HWINT_H. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d1f23388a458..8eda2f7bb0d7 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -379,15 +379,15 @@
(const_int 1)
(and (eq_attr "isa" "p5")
- (match_test "TARGET_POWER5"))
+ (match_test "TARGET_POPCNTB"))
(const_int 1)
(and (eq_attr "isa" "p6")
- (match_test "TARGET_POWER6"))
+ (match_test "TARGET_CMPB"))
(const_int 1)
(and (eq_attr "isa" "p7")
- (match_test "TARGET_POWER7"))
+ (match_test "TARGET_POPCNTD"))
(const_int 1)
(and (eq_attr "isa" "p7v")
@@ -403,7 +403,7 @@
(const_int 1)
(and (eq_attr "isa" "p9")
- (match_test "TARGET_POWER9"))
+ (match_test "TARGET_MODULO"))
(const_int 1)
(and (eq_attr "isa" "p9v")
@@ -2466,7 +2466,7 @@
rtx tmp2 = gen_reg_rtx (<MODE>mode);
rtx tmp3 = gen_reg_rtx (<MODE>mode);
- if (TARGET_POWER7)
+ if (TARGET_POPCNTD)
{
emit_insn (gen_add<mode>3 (tmp1, operands[1], constm1_rtx));
emit_insn (gen_one_cmpl<mode>2 (tmp2, operands[1]));
@@ -2510,7 +2510,7 @@
(define_expand "popcount<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POWER5 || TARGET_POWER7"
+ "TARGET_POPCNTB || TARGET_POPCNTD"
{
rs6000_emit_popcount (operands[0], operands[1]);
DONE;
@@ -2520,14 +2520,14 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_POPCNTB))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB"
"popcntb %0,%1"
[(set_attr "type" "popcnt")])
(define_insn "popcntd<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"popcnt<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2535,7 +2535,7 @@
(define_expand "parity<mode>2"
[(set (match_operand:GPR 0 "gpc_reg_operand")
(parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
- "TARGET_POWER5"
+ "TARGET_POPCNTB"
{
rs6000_emit_parity (operands[0], operands[1]);
DONE;
@@ -2544,7 +2544,7 @@
(define_insn "parity<mode>2_cmpb"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_PARITY))]
- "TARGET_POWER6"
+ "TARGET_CMPB && TARGET_POPCNTB"
"prty<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2597,7 +2597,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
- "TARGET_POWER6"
+ "TARGET_CMPB"
"cmpb %0,%1,%2"
[(set_attr "type" "cmp")])
@@ -3457,7 +3457,7 @@
|| INTVAL (operands[2]) <= 0
|| (i = exact_log2 (INTVAL (operands[2]))) < 0)
{
- if (!TARGET_POWER9)
+ if (!TARGET_MODULO)
FAIL;
operands[2] = force_reg (<MODE>mode, operands[2]);
@@ -3491,7 +3491,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
(mod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
(match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
- "TARGET_POWER9 && !RS6000_DISABLE_SCALAR_MODULO"
+ "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
"mods<wd> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
@@ -3502,7 +3502,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand")
(umod:GPR (match_operand:GPR 1 "gpc_reg_operand")
(match_operand:GPR 2 "gpc_reg_operand")))]
- "TARGET_POWER9"
+ "TARGET_MODULO"
{
if (RS6000_DISABLE_SCALAR_MODULO)
{
@@ -3520,7 +3520,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
(umod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
(match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
- "TARGET_POWER9 && !RS6000_DISABLE_SCALAR_MODULO"
+ "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
"modu<wd> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
@@ -3536,7 +3536,7 @@
(set (match_operand:GPR 3 "gpc_reg_operand")
(mod:GPR (match_dup 1)
(match_dup 2)))]
- "TARGET_POWER9
+ "TARGET_MODULO
&& ! reg_mentioned_p (operands[0], operands[1])
&& ! reg_mentioned_p (operands[0], operands[2])
&& ! reg_mentioned_p (operands[3], operands[1])
@@ -3558,7 +3558,7 @@
(set (match_operand:GPR 3 "gpc_reg_operand")
(umod:GPR (match_dup 1)
(match_dup 2)))]
- "TARGET_POWER9
+ "TARGET_MODULO
&& ! reg_mentioned_p (operands[0], operands[1])
&& ! reg_mentioned_p (operands[0], operands[2])
&& ! reg_mentioned_p (operands[3], operands[1])
@@ -5171,7 +5171,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_POWER5X
+ && TARGET_FPRND
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -5189,7 +5189,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
"TARGET_HARD_FLOAT
- && TARGET_POWER5X
+ && TARGET_FPRND
&& flag_unsafe_math_optimizations"
{
rtx div = gen_reg_rtx (<MODE>mode);
@@ -5401,7 +5401,7 @@
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
- || TARGET_POWER6
+ || TARGET_CMPB
|| VECTOR_UNIT_VSX_P (<MODE>mode))"
{
/* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5422,7 +5422,7 @@
if (!gpc_reg_operand (operands[2], <MODE>mode))
operands[2] = copy_to_mode_reg (<MODE>mode, operands[2]);
- if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))
+ if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
{
emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
operands[2]));
@@ -5438,7 +5438,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
- "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
@@ -6687,7 +6687,7 @@
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X
+ "TARGET_HARD_FLOAT && TARGET_FPRND
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@@ -6784,7 +6784,7 @@
/* For those old archs in which SImode can't be hold in float registers,
call lrint<mode>si_di to put the result in DImode then convert it via
stack. */
- if (!TARGET_POWER7)
+ if (!TARGET_POPCNTD)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_lrint<mode>si_di (tmp, operands[1]));
@@ -6799,7 +6799,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=d")
(unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && TARGET_POWER7"
+ "TARGET_HARD_FLOAT && TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6807,7 +6807,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTIW))]
- "TARGET_HARD_FLOAT && !TARGET_POWER7"
+ "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
"fctiw %0,%1"
[(set_attr "type" "fp")])
@@ -6815,7 +6815,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIZ))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIP))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
UNSPEC_FRIM))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FRIN))]
- "TARGET_HARD_FLOAT && TARGET_POWER5X"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"frin %0,%1"
[(set_attr "type" "fp")])
@@ -10122,7 +10122,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10144,7 +10144,7 @@
(compare:SI (match_operand:BLK 1)
(match_operand:BLK 2)))
(use (match_operand:SI 3))])]
- "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10168,7 +10168,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -14435,7 +14435,7 @@
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"bpermd %0,%1,%2"
[(set_attr "type" "popcnt")])
@@ -14813,7 +14813,7 @@
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")]
UNSPEC_ADDG6S))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"addg6s %0,%1,%2"
[(set_attr "type" "integer")])
@@ -14821,7 +14821,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CDTBCD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cdtbcd %0,%1"
[(set_attr "type" "integer")])
@@ -14829,7 +14829,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CBCDTD))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"cbcdtd %0,%1"
[(set_attr "type" "integer")])
@@ -14844,7 +14844,7 @@
(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
(match_operand:GPR 2 "register_operand" "r")]
UNSPEC_DIV_EXTEND))]
- "TARGET_POWER7"
+ "TARGET_POPCNTD"
"div<wd><div_extend> %0,%1,%2"
[(set_attr "type" "div")
(set_attr "size" "<bits>")])
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 9b8e151000b6..94323bd1db26 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -36,14 +36,6 @@ HOST_WIDE_INT rs6000_isa_flags_explicit
TargetSave
HOST_WIDE_INT x_rs6000_isa_flags_explicit
-;; Arch bits that are set via -mcpu=<xxx> but don't have a user -m<processor>
-;; option
-Variable
-HOST_WIDE_INT rs6000_arch_flags = 0
-
-TargetSave
-HOST_WIDE_INT x_rs6000_arch_flags
-
;; Current processor
TargetVariable
enum processor_type rs6000_cpu = PROCESSOR_PPC603
@@ -136,23 +128,17 @@ mmfcrf
Target Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction.
-;; Originally, we used -mpopcntb to indicate ISA 2.2. Keep the switch name,
-;; but change the target macro.
mpopcntb
-Target Mask(POWER5) Var(rs6000_isa_flags)
-Use ISA 2.2 (Power5) instructions.
+Target Mask(POPCNTB) Var(rs6000_isa_flags)
+Use PowerPC V2.02 popcntb instruction.
-;; Originally, we used -mfprnd to indicate ISA 2.4. Keep the switch name,
-;; but change the target macro.
mfprnd
-Target Mask(POWER5X) Var(rs6000_isa_flags)
-Use ISA 2.2 (Power5x) instructions.
+Target Mask(FPRND) Var(rs6000_isa_flags)
+Use PowerPC V2.02 floating point rounding instructions.
-;; Originally, we used -mcmpb to indicate ISA 2.5. Keep the switch name,
-;; but change the target macro.
mcmpb
-Target Mask(POWER6) Var(rs6000_isa_flags)
-Use ISA 2.5 (Power6) instructions.
+Target Mask(CMPB) Var(rs6000_isa_flags)
+Use PowerPC V2.05 compare bytes instruction.
;; This option existed in the past, but now is always off.
mno-mfpgpr
@@ -196,11 +182,9 @@ mhard-float
Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point.
-;; Originally, we used -mpopcntd to indicate ISA 2.6. Keep the switch name,
-;; but change the target macro.
mpopcntd
-Target Mask(POWER7) Var(rs6000_isa_flags)
-Use ISA 2.6 (Power7) instructions.
+Target Mask(POPCNTD) Var(rs6000_isa_flags)
+Use PowerPC V2.06 popcntd instruction.
mfriz
Target Var(TARGET_FRIZ) Init(-1) Save
@@ -549,11 +533,9 @@ mpower9-minmax
Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
Use the new min/max instructions defined in ISA 3.0.
-;; Originally, we used -mmodulo to indicate ISA 3.0. Keep the switch name,
-;; but change the target macro.
mmodulo
-Target Undocumented Mask(POWER9) Var(rs6000_isa_flags)
-Use ISA 3.0 (Power9) instructions.
+Target Undocumented Mask(MODULO) Var(rs6000_isa_flags)
+Generate the integer modulo instructions.
mfloat128
Target Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
