On Tue, 1 Jun 2021 at 13:37, Schweikhardt, Jens (TSPCE3-TL4)
wrote:
>
> Hesham Almatary wrote:
>
> > You might be confusing taking BASE[XLEN-1:2] (see Figure 3.8) with shifting
> > an address by 2. RTEMS aligns _RISCV_Exception_handler to 4 bytes as per
> > the spe
Hello Jens,
On Tue, 1 Jun 2021 at 12:05, Schweikhardt, Jens (TSPCE3-TL4)
wrote:
>
> hello world,
>
> I'm scratching my head over what may turn out to be a glitch in
> Volume 2, Privileged Spec v. 20190608 RISC-V
> https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Pri
There is also a BSP contributed by SiFive [1] to run on Freedom E310
Arty A7 FPGA.
I am expecting a BeagleV board [2] as well and I'll work on porting
RTEMS to it soon.
[1] https://devel.rtems.org/ticket/3785
[2] https://beagleboard.org/beaglev
On Thu, 22 Apr 2021 at 18:00, Joel Sherrill wrote
On Wed, 25 Nov 2020 at 15:41, wrote:
> Hello,
>
> I tried to experiment a bit with the riscv BSPs.
> I could run them using the SIS simulator, but failed with qemu.
> Regarding qemu I found this ticket:
> https://devel.rtems.org/ticket/3608
>
> In one mailinglist thread (from 2018) someone said i
On Mon, 7 Sep 2020 at 11:05, Schweikhardt, Jens (TSPCE3-TL4)
wrote:
>
> hello world\n
>
>
>
> I’m looking at
> https://git.rtems.org/rtems/tree/bsps/riscv/shared/start/start.S which
> contains near the end
>
>
>
> /* Wait for go issued by the boot processor (mhartid == 0) */
>
>
Hi Rehab,
On Tue, 2 Jan 2018 at 11:26 pm, Rehab Massoud
wrote:
> Hi all,
>
> as in https://devel.rtems.org/wiki/TBR/UserManual/Simulators
> Qemu mips/malta - is said to work with -M malta option. But when I tried
> different variants of qemu-mips, I get either a segmentation fault,
> architectur
