Hello Jens, On Tue, 1 Jun 2021 at 12:05, Schweikhardt, Jens (TSPCE3-TL4) <jens.schweikha...@tesat.de> wrote: > > hello world, > > I'm scratching my head over what may turn out to be a glitch in > Volume 2, Privileged Spec v. 20190608 RISC-V > https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf > > In particular, the way RTEMS for RISCV sets the machine trap vector > in src/rtems/bsps/riscv/shared/start/start.S with > > LADDR t0, _RISCV_Exception_handler > csrw mtvec, t0 > > i.e. loads the 32 bit address _RISCV_Exception_handler into mtvec. > This seems to contradict the layout oft he mtvec register documented in 3.1.7 > as > > mtvec: 30 bits of BASE, 2 bits of MODE. > That might be where the confusion is. BASE is 32-bit, and as per the same section "must always be aligned on a 4-byte boundary." So, you always end up with BASE[1:0] bits = 0 (to be used for MODE bits). Thus, you don't do any shifting of addresses.
> > in conjunction with Table 3.5, MODE 0, "All exceptions set pc to BASE". > > This would set pc to _RISCV_Exception_handler *divided by 4* and probably > crash. > > So either RTEMS writes the wrong value to mtvec, or the RISC-V docs should > say "All exceptions set pc to BASE x 4". > Am I missing something? > You might be confusing taking BASE[XLEN-1:2] (see Figure 3.8) with shifting an address by 2. RTEMS aligns _RISCV_Exception_handler to 4 bytes as per the specification, so you'd always end up with an address with zeros in the least significant 2 bits. So, BASE[1:0] will always be zero. When you write that to mtvec, you'll effectively set the MODE to 0 (Direct), and BASE[XLEN-1:2] will be placed as is in mtvec. I hope that clarifies things up a bit. > > Jens > > ________________________________ > > Tesat-Spacecom GmbH & Co. KG > Sitz: Backnang; Registergericht: Amtsgericht Stuttgart HRA 270977 > Persoenlich haftender Gesellschafter: Tesat-Spacecom Geschaeftsfuehrungs GmbH; > Sitz: Backnang; Registergericht: Amtsgericht Stuttgart HRB 271658; > Geschaeftsfuehrung: Dr. Marc Steckling, Kerstin Basche, Ralf Zimmermann > > [banner] > _______________________________________________ > users mailing list > users@rtems.org > http://lists.rtems.org/mailman/listinfo/users -- Hesham _______________________________________________ users mailing list users@rtems.org http://lists.rtems.org/mailman/listinfo/users
