** Changed in: qemu
Status: Incomplete => Invalid
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https://bugs.launchpad.net/bugs/1863526
Title:
NVIC CCR register not 8-bit accessible using Cortex-M4
Status in QEMU:
Inval
Architecturally the CCR is not byte-accessible. The v7M Arm ARM defines
in B3.1.1 "General rules for PPB register accesses" that unless
otherwise stated, register support word accesses only, and the CCR
register definition does not say that byte access is supported. This is
true also in v8M, where
I am not sure this register can not be accessed differently than 32-bit.
Still I used this patch as a kludge, but it doesn't seem a clean fix:
-- >8 --
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2160,6 +2161,10 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
