&rprr_gather_load u=0 ff=0 xs=2 esz=4 msz=4 scale=0
+&rprr_gather_load u=1 ff=0 xs=2 esz=4 msz=4 scale=0
# SVE 64-bit gather load (vector plus immediate)
LD1_zpiz1100010 .. 01 . 1.. ... . ..... \
Reviewed-by: Richard Henderson
r~
insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson
r~
a[s] = (pg >> e) & 1 ? nn : IDENT; \
} \
*(TYPE *)(vd + H(e)) = FUNC##_reduce(data, status, segments); \
Reviewed-by: Richard Henderson
r~
(s->fpcr_ah ? fminqv_ah_fns : fminqv_fns)[a->esz], a, 0,
a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
/*
Whoopsie.
Reviewed-by: Richard Henderson
r~
er Maydell
---
target/arm/tcg/sve.decode | 2 ++
target/arm/tcg/translate-sve.c | 25 -
2 files changed, 18 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson
r~
ff-by: Peter Maydell
---
target/arm/tcg/helper-sve.h| 14 +++
target/arm/tcg/sve_helper.c| 69 ++
target/arm/tcg/translate-sve.c | 21 ---
3 files changed, 98 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
es changed, 27 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
1 deletion(-)
Reviewed-by: Richard Henderson
r~
et/arm/tcg/translate-sve.c | 22 +-
3 files changed, 32 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
g/helper.h| 3 +++
target/arm/tcg/translate-sve.c | 6 +-
target/arm/tcg/vec_helper.c| 3 +++
3 files changed, 11 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 7/18/25 12:11, Peter Maydell wrote:
On Fri, 18 Jul 2025 at 18:46, Richard Henderson
wrote:
There is no such thing as vector extract.
Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036
Sig
There is no such thing as vector extract.
Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
by_vmid_s1, &vmid);
Reviewed-by: Richard Henderson
r~
On 7/17/25 05:32, Mark Cave-Ayland wrote:
I think the basic Debian toolchain for 32-bit SPARC is working because it is currently
used to build OpenBIOS, so I don't think we're quite at deprecation point yet.
Bear in mind that a cross-compiler for firmware may not have all of the runtime librari
On Wed, 16 July 2025, 10:50 Pierrick Bouvier,
wrote:
> Do you plan to merge FEAT_MEC for 10.1, or prefer to wait for 10.2?
>
We have missed the soft freeze window. It must wait for 10.2 now.
r~
>
/functional/test_aarch64_rme_virt.py | 9 +
3 files changed, 15 insertions(+), 12 deletions(-)
Thanks.
Reviewed-by: Richard Henderson
Tested-by: Richard Henderson
and queued with FEAT_MEC. I'll re-post at some point closer to opening of the
10.2 tree.
r~
+-
accel/tcg/monitor.c | 3 ++-
accel/tcg/tcg-stats.c | 7 +++
3 files changed, 6 insertions(+), 6 deletions(-)
I suppose you could at the same time rename to tcg_get_stats to match the accel hook. But
either way,
Reviewed-by: Richard Henderson
r~
100644 accel/tcg/tcg-stats.c
Reviewed-by: Richard Henderson
r~
On 7/15/25 07:06, Philippe Mathieu-Daudé wrote:
On 15/7/25 14:48, Richard Henderson wrote:
On 7/15/25 04:40, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-all.c | 6 ++
1 file changed, 6 insertions(+)
Oh, this is
On 7/15/25 04:40, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-all.c | 6 ++
1 file changed, 6 insertions(+)
Oh, this is what causes tcg-stats to be used by user-only binaries, is it?
diff --git a/accel/tcg/tcg
On 7/15/25 04:40, Philippe Mathieu-Daudé wrote:
Statistic code is not specific to system emulation (except
cross-page checks) and can be used to analyze user-mode binaries.
But it's not callable from user-mode. At least so far, and within this series.
So, split out the new file if you like, bu
)
rr_deal_with_unplugged_cpus();
}
-rcu_unregister_thread();
-
g_assert_not_reached();
}
Reviewed-by: Richard Henderson
r~
On 7/14/25 11:43, Vacha Bhavsar wrote:
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 64ee9b3b56..c39d636caa 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -228,6 +228,87 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf,
int reg)
return 0;
deletions(-)
Reviewed-by: Richard Henderson
Commit 4e035201 was in 9.2.0, but indeed there's no point in backporting to any
stable branch.
r~
6-5-gustavo.rom...@linaro.org>
Reviewed-by: Richard Henderson
[rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.]
Signed-off-by: Richard Henderson
---
target/arm/cpu-features.h | 5 +++
target/arm/cpu.h | 2 ++
target/arm/internals.h| 19 ++
target/arm
From: Gustavo Romero
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and
SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx
ones.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
Message-ID: <20250711140828.1714666-4-gustavo.rom...@linaro.org>
6-3-gustavo.rom...@linaro.org>
Reviewed-by: Richard Henderson
[rth: Squash 3 patches to add all registers at once.]
Signed-off-by: Richard Henderson
---
target/arm/cpu-features.h | 5 ++
target/arm/cpu.h | 10
target/arm/internals.h| 3 ++
target/arm/cpu.c | 3 ++
Changes for v8:
- Re-order SCTLR2 and TCR2 so that they are independent of MEC.
- Enable the SCTLR2 and TCR2 enable bits.
- Squash 3 smaller MEC patches together.
This still fails the RME tests, because we still need TF-A rebuilt
with ENABLE_FEAT_SCTLR2 and ENABLE_FEAT_TCR2. Pierrick, since
the wrong encryption context is not
possible. An encryption context allow the selection of a memory
encryption engine.
At this point, no real memory encryption is supported, but software
stacks that rely on FEAT_MEC should work properly.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
On 7/14/25 09:41, Pierrick Bouvier wrote:
Indeed, clang does not fold the condition "value && kvm_enabled() && !
kvm_arm_sve_supported()". Looks like a missing case.
This code compiles with gcc -O0, but not clang -O0.
extern int f(void);
int main(int argc) {
if (argc && 0)
f();
}
On 7/14/25 07:40, Richard Henderson wrote:
On 7/14/25 07:37, Daniel Henrique Barboza wrote:
GETPC() should always be called from the top level helper, e.g. the
first helper that is called by the translation code. We stopped doing
that in commit 3157a553ec, and then we introduced problems when
helper_mret(), as reported by
[1].
Call GETPC() at the top level helper and pass the value along.
[1]https://gitlab.com/qemu-project/qemu/-/issues/3020
Suggested-by: Richard Henderson
Fixes: 3157a553ec ("target/riscv: Add Smrnmi mnret instruction")
Closes:https://gitlab.com/qemu-project/qem
On 7/11/25 09:51, unis...@quyllur.org wrote:
From: Rot127
Commit 3/3
Signed-off-by: Rot127
---
configs/targets/sparc32plus-linux-user.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/targets/sparc32plus-linux-user.mak
b/configs/targets/sparc32plus-linux-user.mak
index 7a169
On 7/14/25 00:21, Pierrick Bouvier wrote:
On 7/13/25 2:59 PM, Richard Henderson wrote:
On 7/11/25 08:08, Gustavo Romero wrote:
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
These registers are extensions of the TCR_ELx registers and provide
top-level control of the EL10
On 7/11/25 08:08, Gustavo Romero wrote:
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
These registers are extensions of the TCR_ELx registers and provide
top-level control of the EL10 and EL20 translation regimes.
Since the bits in these registers depend on other CPU featu
On 7/11/25 23:02, Richard Henderson wrote:
On 7/11/25 08:08, Gustavo Romero wrote:
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and
SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx
ones.
Because the bits in these registers depend on other CPU features, and
Separate the access_type from the protection check.
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 5 +++--
target/arm/ptw.c | 11 ++-
target/arm/tcg/m_helper.c | 4 ++--
3 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/arm/internals.h
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpregs-at.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c
index 2ff0b3e76f..bebf168997 100644
--- a/target/arm/tcg/cpregs-at.c
+++ b/target/arm/tcg
Rename get_phys_addr_with_space_nogpc for its only
caller, do_ats_write. Drop the MemOp memop argument
as it doesn't make sense in the new context. Replace
the access_type parameter with prot_check.
Signed-off-by: Richard Henderson
---
target/arm/internals.h
The comment about not being included in the summary table
has been out of date for quite a while.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ce981191b3..8c8eea7109 100644
--- a
We are required to skip DB update for AT instructions, and
we are allowed to skip AF updates. Choose to skip both.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index
Implement FEAT_ATS1A and enable for -cpu max.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h | 1 +
target/arm/cpu-features.h | 5
target/arm/tcg/cpregs-at.c| 44 +++
target/arm/tcg/cpu64.c| 1 +
docs/system/arm
Do not require read permission when translating addresses
for debugging purposes.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 1b90e33f52..c7db93b95c 100644
--- a/target/arm
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index c9506aa6d5..1d103b577f 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -408,10
Separate the access_type from the protection check.
Save the trouble of modifying all helper functions
by passing the new data in the control structure.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a
across all functions,
- Replace access_prot with in_prot_check to S1Translate.
r~
Richard Henderson (9):
target/arm: Add prot_check parameter to pmsav8_mpu_lookup
target/arm: Add in_prot_check to S1Translate
target/arm: Skip permission check from
arm_cpu_get_phys_page_attrs_debug
On 7/8/25 16:14, Vacha Bhavsar wrote:
+if (isar_feature_aa64_sme(&cpu->isar)) {
Preferred usage is cpu_isar_feature(aa64_sme, cpu)
Otherwise,
Reviewed-by: Richard Henderson
PS: I tried this myself a few weeks ago and got an error from gdb. I had assumed that gdb
simply
y: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250314124742.4965-1-geo...@ldpreload.com>
---
linux-user/fd-trans.h | 10 ++
linux-user/main.c | 2 ++
2 files changed, 12 insertions(+)
diff --git a/linux-user/fd-trans.h b/linux-user/fd-trans.h
index 910faaf237..e
sigaction.sa_restorer field to.
Unrelated data may be overwritten.
Align qemu-user with the kernel by also dropping sa_restorer support.
Signed-off-by: Thomas Weißschuh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-ID: <20250709-mips-sa-restorer-v1-1-fc17120e4...@t-8ch
o the calls that convert between the
host and target timespec structs.
Coverity: CID 1507104
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250710164355.1296648-1-peter.mayd...@linaro.org>
---
linux-user/syscall.c | 8 ++--
1 f
re in nanosleep
linux-user/gen-vdso: Handle fseek() failure
linux-user/gen-vdso: Don't read off the end of buf[]
linux-user: Use qemu_set_cloexec() to mark pidfd as FD_CLOEXEC
Richard Henderson (2):
fpu: Process float_muladd_negate_result after rounding
tcg: Use uin
Avoid ubsan failure with clang-20,
tcg.h:715:19: runtime error: applying non-zero offset 64 to null pointer
by not using pointers.
Acked-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 6 +++---
tcg/tcg.c | 9
As we are touching the if() statement here, we correct the
indentation.)
Coverity: CID 1508111
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Richard Henderson
Message-ID: <20250711141217.1429412-1-peter.mayd...@linaro.org>
---
about the file being well-formed, but this is OK because
we only run it on the vdso binaries that we create ourselves in the
build process by running the compiler.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <202507101707
s().)
Coverity: CID 1523742
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250710170707.1299926-2-peter.mayd...@linaro.org>
---
linux-user/gen-vdso.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/
Changing the sign before rounding affects the correctness of
the asymmetric rouding modes: float_round_up and float_round_down.
Reported-by: WANG Rui
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
fpu/softfloat.c | 54
Henderson
Signed-off-by: Richard Henderson
Message-ID: <20250710113123.1109461-1-peter.mayd...@linaro.org>
---
linux-user/syscall.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index fc37028597..e1b1476936 100644
--- a/linu
On 7/11/25 08:12, Peter Maydell wrote:
In the linux-user do_fork() function we try to set the FD_CLOEXEC
flag on a pidfd like this:
fcntl(pid_fd, F_SETFD, fcntl(pid_fd, F_GETFL) | FD_CLOEXEC);
This has two problems:
(1) it doesn't check errors, which Coverity complains about
(2) we use
from
pidfd_open()).
(As we are touching the if() statement here, we correct the
indentation.)
Coverity: CID 1508111
Signed-off-by: Peter Maydell
---
linux-user/syscall.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
Avoid ubsan failure with clang-20,
tcg.h:715:19: runtime error: applying non-zero offset 64 to null pointer
by not using pointers.
Cc: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
Supercedes: 20250618183759.9197-1-...@linux.ibm.com
("[PATCH v2] tcg: Remove NULL arithmet
On 5/6/25 11:34, Jon Wilson wrote:
+case MADV_DONTDUMP:
+if (len > 0) {
+/*
+ * To set the page permissons, we must OR our new flags with the
+ * existing flags. Only mark the pages as PAGE_DONTDUMP if the
+ * entire range has the same f
ans.h | 10 ++
linux-user/main.c | 2 ++
2 files changed, 12 insertions(+)
Reviewed-by: Richard Henderson
and queued, thanks.
r~
On 7/9/25 14:57, Thomas Weißschuh wrote:
The Linux kernel dropped support for sa_restorer on O32 MIPS in the
release 2.5.48 because it was unused. See the comment in
arch/mips/include/uapi/asm/signal.h.
Applications using the kernels UAPI headers will not reserve enough
space for qemu-user to co
2 encoding right
* we implement DBGDTR_EL0 at its correct encoding
Cc:qemu-sta...@nongnu.org
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/2986
Signed-off-by: Peter Maydell
---
target/arm/debug_helper.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
Reviewed-b
On 7/10/25 11:07, Peter Maydell wrote:
These two small patches improve the error handling in the gen-vdso
program. Error handling isn't particularly critical here because
the tool only gets run during the QEMU build process on input
that we trust (because we generated it by calling a compiler
for
insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index fc37028597c..c600d5ccc0e 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -11630,10 +11630,14 @@ static abi_long do_syscall1(CPUArchState *cpu_env
On 7/10/25 05:31, Peter Maydell wrote:
The fchmodat2 syscall is new from Linux 6.6; it is like the
existing fchmodat syscall except that it takes a flags parameter.
Signed-off-by: Peter Maydell
---
v1->v2: don't bother with trying to fall back to libc fchmodat();
add missing braces for if()
Q
On 7/10/25 10:43, Peter Maydell wrote:
target_to_host_timespec() returns an error if the memory the guest
passed us isn't actually readable. We check for this everywhere
except the callsite in the TARGET_NR_nanosleep case, so this mistake
was caught by a Coverity heuristic.
Add the missing erro
dd.
---
linux-user/gen-vdso.c | 5 +
1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson
r~
y thing and use g_file_get_contents().)
Coverity: CID 1523742
Signed-off-by: Peter Maydell
---
linux-user/gen-vdso.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
This function isn't used.
Resolves: Coverity CID 1612139
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper.h | 1 -
target/arm/tcg/vec_helper.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper.h
index d9565c8069..0a006d9514 1
implemented as NOPs too.
Signed-off-by: Gustavo Romero
---
target/arm/helper.c | 24
1 file changed, 24 insertions(+)
Reviewed-by: Richard Henderson
r~
On 7/10/25 10:38, Gustavo Romero wrote:
+static CPAccessResult sctlr2_el2_access(CPUARMState *env,
+const ARMCPRegInfo *ri,
+bool isread)
+{
+if (arm_current_el(env) < 3 && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) {
+
On 7/10/25 10:38, Gustavo Romero wrote:
+static CPAccessResult tcr2_el2_access(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+if (arm_current_el(env) < 3 && !(env->cp15.scr_el3 & SCR_TCR2EN)) {
+return CP_ACCESS_TRAP_EL3;
+}
Sti
s for if()
---
linux-user/syscall.c | 13 +
1 file changed, 13 insertions(+)
Reviewed-by: Richard Henderson
r~
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index fc37028597c..e1b1476936c 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -790,6
On 7/10/25 06:01, Peter Maydell wrote:
On Mon, 7 Jul 2025 at 21:58, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a11df31b18..78a9c21fab
On 7/10/25 05:59, Peter Maydell wrote:
On Mon, 7 Jul 2025 at 22:01, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 39ecc093a5
On 7/9/25 12:03, Gustavo Romero wrote:
At this point, no real memory encryption is supported, but most software
stacks that rely on FEAT_MEC to run should work properly.
s/most //?
Anyway,
Reviewed-by: Richard Henderson
r~
On 7/9/25 12:03, Gustavo Romero wrote:
This commit implements the two cache maintenance instructions introduced
by FEAT_MEC, DC CIPAE and DC CIGDPAE.
Because QEMU does not model the cache topology, all cache maintenance
instructions are implemented as NOPs, hence these new instructions are
imple
On 7/9/25 12:03, Gustavo Romero wrote:
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
These registers are extensions of the TCR_ELx registers and provide
top-level control of the EL10 and EL20 translation regimes.
Since the bits in these registers depend on other CPU featur
On 7/9/25 12:03, Gustavo Romero wrote:
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 552d8757b7..44d6b655a9 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -416,6 +416,11 @@ static inline bool isar_feature_aa64_rdm(const
ARMISARegisters *id)
,
+bool isread)
+{
+if (arm_current_el(env) < 3 && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) {
+return CP_ACCESS_TRAP_EL3;
+}
+return CP_ACCESS_OK;
+};
Stray ;
And on every other function until sctlr2_reginfo.
Otherwise,
Reviewed-by: Richard Henderson
r~
@@ FIELD(MFAR, FPA, 12, 40)
FIELD(MFAR, NSE, 62, 1)
FIELD(MFAR, NS, 63, 1)
+#define MECID_WIDTH 16
This could go in internals.h.
Otherwise,
Reviewed-by: Richard Henderson
r~
id_mask = 0;
+
+if (cpu_isar_feature(aa64_mec, env_archcpu(env))) {
+valid_mask |= SCTLR2_EMEC;
+}
+value &= valid_mask;
+raw_write(env, ri, value);
+};
Stray ;
+
+static void sctlr2_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+uint64_t valid_mask = 0;
+
+if (cpu_isar_feature(aa64_mec, env_archcpu(env))) {
+valid_mask |= SCTLR2_EMEC;
+}
+value &= valid_mask;
+raw_write(env, ri, value);
+};
Stray ;
Otherwise,
Reviewed-by: Richard Henderson
r~
On 7/8/25 10:10, Peter Maydell wrote:
You could argue that the fallback-to-libc-fchmodat here isn't
worth bothering with, I guess.
Indeed not. Support for fchmodat2 is at least 2 years old already.
r~
eviewed-by: Richard Henderson
r~
1 file changed, 13 deletions(-)
Reviewed-by: Richard Henderson
r~
On 7/8/25 11:19, Philippe Mathieu-Daudé wrote:
+/**
+ * target_endian_mode:
+ *
+ * Returns: QAPI EndianMode enum (i.e. ENDIAN_MODE_LITTLE).
s/i.e./e.g./
Otherwise,
Reviewed-by: Richard Henderson
r~
.
Reviewed-by: Richard Henderson
r~
On 7/8/25 11:19, Philippe Mathieu-Daudé wrote:
Check endianness at runtime to remove the target-specific
TARGET_BIG_ENDIAN definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/gdbstub/helpers.h | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/inclu
On 7/7/25 11:20, Philippe Mathieu-Daudé wrote:
When we'll start to use target_machine_typename() to filter
machines for the ARM/Aarch64 binaries, the 'none' machine
would be filtered out. Register the proper interfaces to keep
it available.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pie
On 7/7/25 11:20, Philippe Mathieu-Daudé wrote:
While DEFINE_MACHINE() is a succinct macro, it doesn't
allow registering QOM interfaces to the defined machine.
Convert to the generic DEFINE_TYPES() in preparation to
register interfaces.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpregs-at.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c
index e79866e651..39141c83aa 100644
--- a/target/arm/tcg/cpregs-at.c
+++ b/target/arm/tcg
Implement FEAT_ATS1A and enable for -cpu max.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h | 1 +
target/arm/cpu-features.h | 5
target/arm/tcg/cpregs-at.c| 44 +++
target/arm/tcg/cpu64.c| 1 +
docs/system/arm
Rename get_phys_addr_with_space_nogpc for its only
caller, do_ats_write. Drop the MemOp memop argument
as it doesn't make sense in the new context.
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 17 +++--
target/arm/ptw.c | 17 ++---
t
Complete the conversion of all routines in ptw.c from
MMUAccessType access_type to an access_perm bitmask.
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 4 ++--
target/arm/ptw.c | 4 ++--
target/arm/tcg/m_helper.c | 8
3 files changed, 8 insertions(+), 8
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 4 ++--
target/arm/ptw.c | 4 ++--
target/arm/tcg/cpregs-at.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1781943fac..20b49201cb 100644
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index fef9e9a7cb..adc681da41 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -80,7 +80,7 @@ static bool
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 2 +-
target/arm/ptw.c | 6 +++---
target/arm/tcg/m_helper.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c4765e4489..629aa7bc23 100644
--- a
Because of the recursion with get_phys_addr_twostage,
we must convert the two functions at the same time.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 39 ---
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/target/arm/ptw.c b/target
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