On 7/14/25 00:21, Pierrick Bouvier wrote:
On 7/13/25 2:59 PM, Richard Henderson wrote:
On 7/11/25 08:08, Gustavo Romero wrote:
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers.
These registers are extensions of the TCR_ELx registers and provide
top-level control of the EL10 and EL20 translation regimes.
Since the bits in these registers depend on other CPU features, and only
FEAT_MEC is supported at the moment, the FEAT_TCR2 only implements the
AMEC bits for now.
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
This causes a regression in
tests/functional/test_aarch64_device_passthrough.py, by
continually trapping on an access to TCR2_EL1 while the HCRX_EL2 enable bit is
not set.
Unlike the similar SCTRL2 failure, it's not 100% clear to me how the guest and
nested
guest kernels are related. But it is clear that the outer kernel does not does
not
support TCR2_EL1 (and also doesn't manipulate ID_AA64MMFR3_EL1 to hide
FEAT_TCR2), but the
nested guest kernel does support TCR2_EL1.
The same kernel is used for host and guest.
Maybe it's related to kvm support?
Oops, no, the patch fails to enable HCRX_TCR2EN in hcrx_write or SCR_TCR2EN in
scr_write.
The same is true for the previous patch with HCRX_SCTLR2EN and SCR_SCTLR2EN.
r~
