On 7/8/25 05:52, Peter Maydell wrote:
The GIC distributor registers GICD_TYPER2 is present when the
GICv4.1 is implemented, and RES0 otherwise. QEMU's TCG implementation
is only GICv4.0, so this register is RES0. However, since it's
reasonable for GICv4.1-aware software to read the register, expecting
the zero for GICv3 and GICv4.0, implement the case to avoid it being
logged as an invalid guest read.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
---
hw/intc/gicv3_internal.h | 1 +
hw/intc/arm_gicv3_dist.c | 9 +++++++++
2 files changed, 10 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
