On Sun, Jul 6, 2025 at 11:04 PM Vac Chen wrote:
>
> pmp_is_in_range() prefers to match addresses within the interval
> [start, end]. To archieve this, pmpaddrX is decremented during the end
> address update.
>
> In TOR mode, a rule is ignored if its start address is greater than or
> equal to its
issue by moving the guard check earlier,
> preventing the problematic wraparound when pmpaddrX is zero.
>
> Signed-off-by: Vac Chen
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmp.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --g
On Tue, Jun 17, 2025 at 4:29 PM ~liuxu wrote:
>
> Thanks for Alistair's correction on the V8 version.
>
> Now Zclsd has been disabled for the "max" CPU as C and F are already
> enabled.
This is still broken with userspace mode:
```
qemu-riscv64: Zclsd cannot be supported together with C and F ex
On Wed, Jul 2, 2025 at 5:31 PM Alexandre Ghiti wrote:
>
> The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
> for software to use.
>
> Reviewed-by: Deepak Gupta
> Signed-off-by: Alexandre Ghiti
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Changes in v2:
>
other
> archs.
>
> Cc: Dr. David Alan Gilbert
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> monitor/hmp-cmds-target.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/monitor/hmp-cmds-target.c b
On Thu, Jun 19, 2025 at 7:36 AM Vasilis Liaskovitis
wrote:
>
> Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1
> and rd arguments are x0.
>
> In this case, if the new property is true, only the vill bit will be set.
>
> See
> https://github.com/riscv/riscv-isa-manual
.net/wiki/spaces/HOME/pages/16154882/All+RISC-V+Specifications+Under+Active+Development
>
> Signed-off-by: Roan Richmond
> ---
>
> Ping! resending this as no movement on previous send.
>
> V3:
> - rebased patch onto master branch
> - added check for aq on Load Acquire
.net/wiki/spaces/HOME/pages/16154882/All+RISC-V+Specifications+Under+Active+Development
>
> Signed-off-by: Roan Richmond
Reviewed-by: Alistair Francis
Alistair
> ---
>
> Ping! resending this as no movement on previous send.
>
> V3:
> - rebased patch onto master branch
On Tue, Jun 17, 2025 at 4:29 PM ~liuxu wrote:
>
> Thanks for Alistair's correction on the V8 version.
>
> Now Zclsd has been disabled for the "max" CPU as C and F are already
> enabled.
>
> lxx (1):
> target/riscv: Add Zilsd and Zclsd extension support
Thanks!
Applied to riscv-to-apply.next
A
On Fri, Jul 4, 2025 at 4:24 AM Charalampos Mitrodimas
wrote:
>
> This patch series fixes incorrect behavior in MEPC/SEPC CSRs where the
> lower bits were not properly masked according to the RISC-V specification.
>
> The issue was discovered when vectored mode bits from STVEC were
> written to MEP
, when vectored mode bits from STVEC (which sets bit 0 for
> vectored mode) were written to MEPC, the bits would not be cleared
> correctly, causing incorrect behavior on MRET.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2855
> Signed-off-by: Charalampos Mi
On Mon, Jun 16, 2025 at 5:02 PM wrote:
>
> Address an error in migration when aia is configured as 'aplic-imsic' in
> riscv kvm vm by adding riscv_aplic_state_needed() and
> riscv_imsic_state_needed() to determine whether the corresponding sates are
> needed.
>
> Previously, the fields in the vmsd
to migration failure
> characterized by uninitialized fields when save vm state:
> qemu-system-riscv64: ../migration/vmstate.c:433: vmstate_save_state_v:
> Assertion 'first_elem || !n_elems || !size' failed.
>
> Fixes: 95a97b3fd2 ("target/riscv: update APLIC an
On Tue, Jun 24, 2025 at 1:12 PM Jay Chang wrote:
>
> Hi,
>
> Gentle ping on this patch.
Sorry it slipped through. Can you include a cover letter to makes
things easier to manage [1]
1:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#include-a-meaningful-cover-letter
Alistair
>
On Fri, Jun 27, 2025 at 11:31 PM Max Chou wrote:
>
> According to the V spec, the vector fault-only-first load instructions
> may change the VL CSR.
> So the ldff_trans TCG translation function should generate the
> lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to
> make sure
On Fri, Apr 25, 2025 at 10:18 PM Ran Wang wrote:
>
> This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
> platform, which include UART, CLINT, IMSIC, and APLIC
> devices.
>
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Patches based on alistair/riscv-
by: SUN Dongya
> Co-developed-by: ZHAO Fujin
> Reviewed-by: Alistair Francis
This breaks with linux-user (which is using the "max" CPU)
./build/qemu-riscv64 ./images/qemuriscv64/target-rootfs/usr/bin/sha512sum ...
qemu-riscv64: Zclsd cannot be supported together with C and F ex
On Fri, Apr 25, 2025 at 10:22 PM Ran Wang wrote:
>
> From: Huang Borong <3543977...@qq.com>
>
> This implementation provides emulation for the Xiangshan Kunminghu
> FPGA prototype platform, including support for UART, CLINT, IMSIC,
> and APLIC devices. More details can be found at
> https://github
by: SUN Dongya
> Co-developed-by: ZHAO Fujin
> Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c| 4 +
> target/riscv/cpu_cfg_fields.h.inc | 2 +
> target/riscv/insn16.decode
le with `!function=ex_rvc_register`.
You are right!
In future please reply inline and in plain text though.
This is good to go then, do you mind rebasing it on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
sending a v8
Alistair
>
> Alistair Francis 在 2025年6月11日 周三 12:47 写道：
> On T
On Wed, Jun 4, 2025 at 12:58 PM Joel Stanley wrote:
>
> v2:
> - Rebased on master now that Daniel's changes are merged
> - Fixed doubled up patch 1
> - r-b tags from Alistair and Daniel added
>
> This is a set of cleanups for the riscv virt machine device tree
> generation.
>
> Using dumpdtb th
On Wed, Jun 11, 2025 at 7:33 PM Roan Richmond
wrote:
>
>
> On 11/06/2025 05:29, Alistair Francis wrote:
> > On Tue, Jun 10, 2025 at 6:33 PM Roan Richmond
> > wrote:
> >> This is based on version v0.8.3 of the ZALASR specification [1].
> >> The specif
isasContext *ctx, arg_sd *a)
> +{
> +if ((a->rs2) % 2) {
> +return false;
> +}
> +
> +TCGv data_low = get_gpr(ctx, a->rs2, EXT_NONE);
> +TCGv data_high = get_gpr(ctx, a->rs2 + 1, EXT_NONE);
> +TCGv addr = get_address(ctx, a->rs1, a->imm);
>
On Tue, Jun 10, 2025 at 6:33 PM Roan Richmond
wrote:
>
> Ping, resending as no responses in over week.
>
> V2:
> - rebased patch onto master branch
> - added check for RV64() for Load Double, as pointed out by Alistair Palmer.
>
> In response to Alistair Palmer
> (https://lists.gnu.org/archiv
On Tue, Jun 10, 2025 at 6:33 PM Roan Richmond
wrote:
>
> This is based on version v0.8.3 of the ZALASR specification [1].
> The specification is listed as in Frozen state [2].
>
> [1]: https://github.com/riscv/riscv-zalasr/tree/v0.8.3
> [2]:
> https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages
On Mon, Jun 2, 2025 at 11:14 PM Djordje Todorovic
wrote:
>
> Several things implemented in v2:
> - Addressing review comments
> - Simplify `target/riscv/xmips.decode`
> - Rebase on top of latest master
> - Fix code format
>
> Djordje Todorovic (9):
> hw/intc: Allow gaps in hartids for
On Mon, Jun 2, 2025 at 11:13 PM Djordje Todorovic
wrote:
>
> Add a network device e1000e to the boston-aia board model.
> There is no pch_gbe emulation, so we add e1000e in slot 0 func 1,
> instead. We need to pass func to call pci_parse_devaddr to find
> out slot and func.
>
> Signed-off-by: Chao
On Mon, Jun 2, 2025 at 11:13 PM Djordje Todorovic
wrote:
>
> Add mips.ccmov defined by Xmipscmov.
>
> Signed-off-by: Chao-ying Fu
> Signed-off-by: Djordje Todorovic
> ---
> target/riscv/cpu.c| 3 ++
> target/riscv/cpu_cfg.h| 5 +++
> target/riscv/cp
On Tue, Jun 10, 2025 at 5:42 PM Philippe Mathieu-Daudé
wrote:
>
> On 2/6/25 15:12, Djordje Todorovic wrote:
> > Define MIPS CSRs used for P8700 CPU.
> >
> > Signed-off-by: Chao-ying Fu
> > Signed-off-by: Djordje Todorovic
> > ---
> > target/riscv/cpu.c | 3 +
> > target/riscv/cpu.h
On Mon, Jun 2, 2025 at 11:15 PM Djordje Todorovic
wrote:
>
> Add a new function, so we can change reset vector from platforms.
You can use the "resetvec" property instead, there are a range of
RISC-V machines already doing this. Have a look at
hw/riscv/opentitan.c or hw/riscv/sifive_u.c for examp
On Mon, Jun 9, 2025 at 11:18 PM Ben Dooks wrote:
>
> Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
>
> Signed-off-by: Ben Dooks
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 11 +++
> 2 files changed, 1
On Mon, Jun 9, 2025 at 11:20 PM Ben Dooks wrote:
>
> Change to using TYPE_RISCV_CPU_CVA6 once this is merged.
You can also just change the patch order to not require this patch
>
> Signed-off-by: Ben Dooks
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/cva6.c
On Mon, Jun 9, 2025 at 11:19 PM Ben Dooks wrote:
>
> Add a (currently Genesy2 based) CVA6 machine.
>
> Has SPI and UART, the GPIO and Ethernet are currently black-holed
> as there is no hardware model for them (lowRISC ethernet and Xilinx
> GPIO)
>
> Signed-off-by: Ben Dooks
> ---
> v3:
> - fix m
On Thu, Jun 5, 2025 at 8:14 PM Florian Lugou
wrote:
>
> The current handler for TXFIFO writes schedules an async callback to
> pop characters from the queue. When software writes to TXFIFO faster
> than the async callback delay (100ns), the timer may be pushed back
> while the previous character h
being infinitly pushed back.
You would hope the guest software doesn't write to the register when
the FIFO is full
>
> This commit fixes the issue by never pushing back the timer, only
> updating it if it is not already active.
The fix looks correct though
>
> Signed-off-by
On Thu, May 1, 2025 at 9:44 PM Anton Blanchard wrote:
>
> fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16
> quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN.
>
> Signed-off-by: Anton Blanchard
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/ri
On Thu, May 1, 2025 at 9:44 PM Anton Blanchard wrote:
>
> fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16
> quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN.
>
> Signed-off-by: Anton Blanchard
Acked-by: Alistair Francis
Alistair
> -
can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Signed-off-by: qinshaoqing
> Signed-off-by: Yang Wang
> Signed-off-by: Yu Hu
> Signed-off-by: Ran Wang
> Signed-off-by: Borong Huang <3543977...@qq.com>
> Reviewed-by: Daniel Henrique Barboza
Acked
On Sat, Jun 7, 2025 at 12:12 PM Chao Liu wrote:
>
> Hi,
>
> Thanks to Daniel's testing, I have fixed this bug.
>
> PATCHv5:
>
> The differences are as follows:
>
> ```
> @@ -790,10 +790,11 @@ static void sifive_u_soc_realize(DeviceState *dev,
> Error **errp)
> MemoryRegion *mask_rom = g_new(
mu_get_cpu(),
> in riscv cpu_by_arch_id() uses the mhartid.
>
> For non-numa or single-cluster machines, hartid_base should be 0.
>
> Signed-off-by: Chao Liu
> Reviewed-by: Tingjian Zhang
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/intc/sifive_plic.c | 4 ++--
&g
On Thu, Jun 5, 2025 at 7:45 PM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this version I removed the reference of SBI_EXT_DBCN_CONSOLE_WRITE in
> the commit message. That API is *non-blocking*, and citing it to justify
> a change in a blocking API sounds weird. It's also uneeded since we have
>
> or used until now, so just remove the definitions. They can be added
> back when really necessary.
>
> Signed-off-by: Zhenzhong Duan
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> include/hw/riscv/iommu.h | 6 ++
> hw/riscv
On Thu, Jun 5, 2025 at 10:50 PM Nutty Liu wrote:
>
> The original implementation incorrectly performed a bitwise AND
> operation between the PPN of iova and PPN Mask, leading to an
> incorrect PPN field in Translation-reponse register.
>
> The PPN of iova should be set entirely in the PPN field of
On Fri, Jun 6, 2025 at 5:28 PM Jay Chang wrote:
>
> Previously, the number of PMP regions was hardcoded to 16 in QEMU.
> This patch replaces the fixed value with a new `pmp_regions` field,
> allowing platforms to configure the number of PMP regions.
>
> If no specific value is provided, the defaul
-by: Jay Chang
> Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 48 +--
> target/riscv/cpu.h| 3 +-
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/riscv/csr.c
On Fri, Jun 6, 2025 at 1:45 PM Meng Zhuo wrote:
>
> This patch adds max_satp_mode from host kvm cpu setting.
>
> Tested on: Milkv Megrez (Eswin 7700x)
>
> Reviewed-by: Andrew Jones
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
> Signed-off-by: Meng Zhuo
Thanks!
Applied to risc
On Thu, Jun 5, 2025 at 3:34 PM Jay Chang wrote:
>
> Hi Daniel,
>
> You're absolutely right — thanks for pointing it out and providing the fix!
>
> Would you like me to send out a v5 patch incorporating your changes?
Yes please
Alistair
>
>
> Best Regards
> Jay Chang
>
>
> On Thu, Jun 5, 2025 at
On Thu, May 8, 2025 at 7:49 PM Jim Shu wrote:
>
> Support 4-byte atomic instruction fetch when instruction is natural
> aligned.
>
> Current implementation is not atomic because it loads instruction twice
> for first and last 2 bytes. We load 4 bytes at once to keep the
> atomicity. This instructi
wants to provide this feature by HW. RVA20U64
> Ziccif protects the atomicity of instruction fetch when it is
> natural aligned.
>
> This commit depends on the atomic read support of translator_ld in
> the commit 6a9dfe1984b0c593fb0ddb52d4e70832e6201dd6.
>
> Signed-off-by: Ji
et/riscv: add 'rva22u64' CPU")
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
> Reviewed-by: Björn Töpel
> Tested-by: Björn Töpel
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 127 +++-
> Signed-off-by: Daniel Henrique Barboza
> Message-ID: <20250529202315.1684198-4-dbarb...@ventanamicro.com>
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/targe
* cpu.debug = true is marked as 'sdtrig', priv spec 1.12.
> + * Skip this warning dince existing CPUs with older priv
since
> + * specd and debug = true will be impacted.
spec
Otherwise:
Reviewed-by: Alistair Francis
Alistair
> + */
> +if
On Wed, May 21, 2025 at 7:21 PM Roan Richmond
wrote:
>
Can you include in the commit message which exact version (please
include a link) of the spec this targets. We need exact versions as
RISC-V will often release multiple conflicting "final" versions, so
it's good to have a record of what this
e chapter
> order in the specifications.
>
> Signed-off-by: Yu Hu
> Signed-off-by: Ran Wang
> Signed-off-by: Borong Huang <3543977...@qq.com>
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> tar
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cd0b159ed5..fdf2eb2b1c 10064
gt;
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9d6fae72b2..cd0b159ed5 100644
> --- a/target/
mu_get_cpu(),
> in riscv cpu_by_arch_id() uses the mhartid.
>
> For non-numa or single-cluster machines, hartid_base should be 0.
>
> Signed-off-by: Chao Liu
> Reviewed-by: Tingjian Zhang
> Reviewed-by: Alistair Francis
Should be:
Reviewed-by: Alistair Francis
Otherw
boza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fe21e0fb44..9d6fae72b2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
>
On Thu, May 29, 2025 at 10:52 PM Nutty Liu
wrote:
>
> The original implementation incorrectly performed a bitwise AND
> operation between the PPN of iova and PPN Mask, leading to an
> incorrect PPN field in Translation-reponse register.
>
> The PPN of iova should be set entirely in the PPN field o
On Fri, May 30, 2025 at 6:24 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> These simple patches add two missing named features in riscv,isa. Third
> patch is a doc change I figured was worth doing.
>
> Drew, as far as Server SoC Reference platform goes, we don't have
> 'sdext'. I guess we'll have
On Fri, May 30, 2025 at 12:01 AM Meng Zhuo wrote:
>
> This patch adds host satp mode while kvm/host cpu satp mode is not
> set.
>
> Reviewed-by: Andrew Jones
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
> Signed-off-by: Meng Zhuo
> ---
> This patch don't change the output of er
On Fri, May 30, 2025 at 11:47 PM Daniel Henrique Barboza
wrote:
>
> These properties were deprecated in QEMU 8.2, commit 8043effd9b.
>
> Signed-off-by: Daniel Henrique Barboza
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 17 -
> target/
On Fri, May 30, 2025 at 11:47 PM Daniel Henrique Barboza
wrote:
>
> These properties were deprecated in QEMU 8.2, commit 8043effd9b.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 17 ---
On Thu, May 22, 2025 at 6:14 PM Jay Chang wrote:
>
> The first patch extends the number of PMP regions supported up to 64,
> following the RISC-V Privileged Specification (version >1.12), where
> RV32 can have up to 64 PMP regions configured through 16 CSRs.
>
> The second patch makes the PMP regi
-by: Jay Chang
> Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 54 +--
> target/riscv/cpu.h| 3 +-
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/riscv/csr.c
On Wed, May 21, 2025 at 3:24 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> The motivation of this short series is to fix a reported in [1]. A
> couple of bugs were fixed along the way.
>
> Björn, these patches should remediate the situation you're experiencing.
>
> Patches based on master.
>
> [1]
>
> [1]
> https://lore.kernel.org/qemu-riscv/87y0usiz22@all.your.base.are.belong.to.us/
>
> Reported-by: Björn Töpel
> Fixes: 2af005d610 ("target/riscv/tcg: validate profiles during finalize")
> Signed-off-by: Daniel Henrique Barboza
>
> Signed-off-by: Daniel
On Wed, May 28, 2025 at 4:13 PM Ethan Chen wrote:
>
> On Thu, May 22, 2025 at 11:24:28AM +1000, Alistair Francis wrote:
> > [EXTERNAL MAIL]
> >
> > On Wed, Mar 12, 2025 at 7:43 PM Ethan Chen via
> > wrote:
> > >
> > > - Add 'iopmp=o
et/riscv: add 'rva22u64' CPU")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 127 +++--
> 1 file changed, 67 insertions(+), 60 deletions(-)
>
> diff --g
ituation where we'll set mmu=on without a virtual
> memory mode, which is a mistake.
>
> Only touch 'mmu' and satp_mode if the profile is being enabled.
>
> Suggested-by: Andrew Jones
> Fixes: 55398025e7 ("target/riscv: add satp_mode profile support")
On Thu, May 22, 2025 at 9:35 PM Daniel Henrique Barboza
wrote:
>
> Put it after zalrsc and before zawrs.
>
> Cc: qemu-triv...@nongnu.org
> Fixes: a60ce58fd9 ("target/riscv: Support Zama16b extension")
> Signed-off-by: Daniel Henrique Barboza
Thanks!
Applied to riscv-to-apply.next
Alistair
> -
On Thu, May 22, 2025 at 9:35 PM Daniel Henrique Barboza
wrote:
>
> Put it after zalrsc and before zawrs.
>
> Cc: qemu-triv...@nongnu.org
> Fixes: a60ce58fd9 ("target/riscv: Support Zama16b extension")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by:
On Wed, Apr 16, 2025 at 3:20 PM Chao Liu wrote:
>
> riscv_plic_hart_config_string() when getting CPUState via qemu_get_cpu()
> should be consistent with keeping sifive_plic_realize()
> by hartid_base + cpu_index.
>
> A better approach is to use cpu_by_arch_id() instead of qemu_get_cpu(),
> in risc
mu_get_cpu(),
> in riscv cpu_by_arch_id() uses the mhartid.
>
> For non-numa or single-cluster machines, hartid_base should be 0.
>
> Signed-off-by: Chao Liu
> Reviewed-by: Qingze Zhao
> Reviewed-by: Tingjian Zhang
Reviewed-by: Alistair Francis
Alistair
> ---
> hw
On Wed, Mar 12, 2025 at 7:43 PM Ethan Chen via wrote:
>
> - Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine
> to protect all regions of system memory.
>
> Signed-off-by: Ethan Chen
> ---
> docs/specs/index.rst | 1 +
> docs/specs/riscv-iopmp.rst | 60 ++
On Wed, Mar 12, 2025 at 7:41 PM Ethan Chen via wrote:
>
> Support IOPMP specification v0.7.
> The specification url:
> https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.7
v10 of the series supported v0.9.2RC3 [1], why is this now 0.7?
We should be targeting the latest version of a draf
t;
> Signed-off-by: Ethan Chen
Acked-by: Alistair Francis
Alistair
> ---
> include/hw/misc/riscv_iopmp_txn_info.h | 38 ++
> 1 file changed, 38 insertions(+)
> create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
>
> diff --git a/include/hw/m
On Fri, Apr 25, 2025 at 7:46 PM Jay Chang wrote:
>
> Previously, the number of PMP regions was hardcoded to 16 in QEMU.
> This patch replaces the fixed value with a new `pmp_regions` field,
> allowing platforms to configure the number of PMP regions.
>
> If no specific value is provided, the defau
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_bits.h | 60 +++
> target/riscv/csr.c | 124 +++-
> 2 files changed, 182 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/
On Tue, May 20, 2025 at 3:08 PM Michael Tokarev wrote:
>
> On 19.05.2025 07:04, alistai...@gmail.com wrote:
> > From: Alistair Francis
>
> > First RISC-V PR for 10.1
> >
> > * Add support for RIMT to virt machine ACPI
> > * Don't allow PMP RLB to bypas
On Tue, May 20, 2025 at 12:36 AM Jim Shu wrote:
>
> This patch series contains several sstc fixes:
>
> (1) Writing to ACLINT mtime should also update the period of S/VS-mode
> timer, just like M-mode timer.
> (2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
> (3) Writing to
On Mon, Apr 28, 2025 at 6:57 PM Meng Zhuo wrote:
>
> This patch adds host satp mode while kvm/host cpu satp mode is not
> set.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
> Signed-off-by: Meng Zhuo
Can you please rebase this on
https://github.com/alistair23/qemu/tree/riscv-t
On Wed, Apr 9, 2025 at 12:53 PM Jim Shu wrote:
>
> This patch series contains several sstc fixes:
>
> (1) Writing to ACLINT mtime should also update the period of S/VS-mode
> timer, just like M-mode timer.
> (2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE.
> (3) Writing to S
On Wed, Apr 9, 2025 at 12:52 PM Jim Shu wrote:
>
> Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
> also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR.
>
> Signed-off-by: Jim Shu
Acked-by: Alistair Francis
Alistair
> ---
>
On Mon, Apr 28, 2025 at 6:57 PM Meng Zhuo wrote:
>
> This patch adds host satp mode while kvm/host cpu satp mode is not
> set.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
> Signed-off-by: Meng Zhuo
Reviewed-by: Alistair Francis
Alistair
> ---
register, whenever (time + htimedelta),
> truncated to 64 bits, contains a value greater than or equal to
> vstimecmp
>
> Signed-off-by: Jim Shu
Acked-by: Alistair Francis
Alistair
> ---
> hw/intc/riscv_aclint.c | 5 +
> 1 file changed, 5 insertions(+)
>
On Tue, May 13, 2025 at 2:33 AM wrote:
>
> From: Xuemei Liu
>
> Address an error in migration when aia is configured as 'aplic-imsic' in
> riscv kvm vm by adding riscv_aplic_state_needed() and
> riscv_imsic_state_needed() to determine whether the corresponding sates are
> needed.
>
> Previously,
On Tue, May 6, 2025 at 8:47 AM Daniel Henrique Barboza
wrote:
>
> Hi Alistair,
>
>
> I think we should push this upstream and see what happens. We'll have a
> full release cycle to undo the change in case we find unintended side
> effects. I'm fairly optimistic that this change will be a no-op for
Reviewed-by: Jerry Zhang Jian
> Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 27edd5af62..f737b703
On Mon, May 5, 2025 at 6:59 AM Richard Henderson
wrote:
>
> Check 32 vs 64-bit and pointer masking state.
>
> Cc: qemu-ri...@nongnu.org
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 26 +++
On Mon, May 12, 2025 at 7:53 PM Paolo Bonzini wrote:
>
> Start putting all the CPU definitions in a struct. Later this will replace
> instance_init functions with declarative code, for now just remove the
> ugly cast of class_data.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by
On Mon, May 12, 2025 at 7:53 PM Paolo Bonzini wrote:
>
> Same as v4, with suggestion from Richard to avoid parentheses---which also
> fixes the issue with kvm-cpu.c reported by Daniel Barboza. KVM/RISC-V is
> now covered in CI and passes with this version.
>
> Paolo
>
> Paolo Bonzini (26):
> ta
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 75 ++
> 1 file changed, 35 insertions(+), 40 deletions(-)
>
> diff
ll registration of properties to .instance_init,
> call accel_cpu_instance_init() at the end of riscv_cpu_init().
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
&
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 80 +-
> 1 file changed, 23 insertions(+), 57 deletions(-)
>
> diff
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 127 +
> 1 file changed, 60 insertions(+), 67 deletions(-)
>
> diff
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 61 +-
> 1 file changed, 28 insertions(+), 33 deletions(-)
>
> diff
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> While at it, constify it so that the RISCVCSR array in RISCVCPUDef
> can also be const.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 15 ---
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> In preparation for generalizing the custom CSR functionality,
> make the test return bool instead of int. Make the insertion_test
> optional, too.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistai
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 79 +++---
> 2 files changed, 37 insertion
1 - 100 of 2332 matches
Mail list logo
