On Thu, Jun 5, 2025 at 3:45 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> We have support for sdtrig for awhile but we are not advertising it. It
> is enabled by default via the 'debug' flag. Use the same flag to also
> advertise sdtrig.
>
> Add an exception in disable_priv_spec_isa_exts() to avoid spamming
> warnings for 'sdtrig' for vendor CPUs like sifive_u.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> ---
>  target/riscv/cpu.c                |   1 +
>  target/riscv/tcg/tcg-cpu.c        |   9 +++++++++
>  tests/data/acpi/riscv64/virt/RHCT | Bin 400 -> 406 bytes
>  3 files changed, 10 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ee3ee0e883..eeb44a2f1e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -189,6 +189,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
>      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> +    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),
>      ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
>      ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 81174de409..7fbfc26adf 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -451,6 +451,15 @@ static void 
> riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
>                  continue;
>              }
>
> +            /*
> +             * cpu.debug = true is marked as 'sdtrig', priv spec 1.12.
> +             * Skip this warning dince existing CPUs with older priv

since

> +             * specd and debug = true will be impacted.

spec

Otherwise:

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> +             */
> +            if (!strcmp(edata->name, "sdtrig")) {
> +                continue;
> +            }
> +
>              isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
>
>              /*
> diff --git a/tests/data/acpi/riscv64/virt/RHCT 
> b/tests/data/acpi/riscv64/virt/RHCT
> index 
> 13c8025b868051485be5ba62974a22971a07bc6a..156607dec45b0e63e5b3ebed62e81076dacd80d0
>  100644
> GIT binary patch
> delta 49
> zcmbQhJdK$v$iq2g8Y2S(<Ex2W2COEGj0`#x?N_s=loVyAPkd23IgL??BZrZJp^TA%
> F0RTq!4730M
>
> delta 43
> zcmbQnJb{@j$iq2g0wV(h<JXB?2CRCFj0~z1?N?9ySUowLQJEu+k%6Irk%0jK_Q(p3
>
> --
> 2.49.0
>
>

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