On Fri, Jul 4, 2025 at 4:24 AM Charalampos Mitrodimas <charmi...@posteo.net> wrote: > > This patch series fixes incorrect behavior in MEPC/SEPC CSRs where the > lower bits were not properly masked according to the RISC-V specification. > > The issue was discovered when vectored mode bits from STVEC were > written to MEPC and not properly cleared, causing incorrect behavior > on MRET. > > Charalampos Mitrodimas (2): > target/riscv: Fix MEPC/SEPC bit masking for IALIGN > tests/tcg/riscv64: Add test for MEPC bit masking
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/csr.c | 8 +-- > target/riscv/internals.h | 11 ++++ > target/riscv/op_helper.c | 4 +- > tests/tcg/riscv64/Makefile.softmmu-target | 4 ++ > tests/tcg/riscv64/test-mepc-masking.S | 73 +++++++++++++++++++++++ > 5 files changed, 94 insertions(+), 6 deletions(-) > create mode 100644 tests/tcg/riscv64/test-mepc-masking.S > > -- > 2.47.2 > >
