Add functional test for Boston AIA board. The P8700 RISC-V based
CPU by MIPS supports it at the moment.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
tests/functional/meson.build| 1 +
tests/functional/test_riscv64_boston.py | 78 +
2
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 15 +++
target/riscv/cpu_vendorid.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu-qom.h b
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/intc/riscv_aclint.c | 21
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 3 ++-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 13 +
target/riscv/cpu.h | 4
2 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu.c b/target
Add support for the Coherent Processing System for RISC-V.
This enables SMP support for RISC-V boards that require
cache-coherent multiprocessor systems.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/misc/Kconfig| 5 ++
hw/riscv/cps.c | 197
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 2 +-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
MIPS BOSTON AIA board.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/misc/Kconfig | 10 ++
hw/misc/meson.build | 2 +
hw/misc/riscv_cmgcr.c | 234 ++
include/hw/misc/riscv_cmgcr.h | 49 +++
4 files
-system-riscv64 -cpu mips-p8700 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv
I addressed several comments in this version, major ones:
- split CPC / CMGCR into separated changes
- split CPS into a separated change
- added functional tests for boston-aia board
Djordje Todorovic (14):
hw/intc: Allow gaps in hartids for aclint and aplic
target/riscv: Add
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 3 +
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 228 +++
4 files changed
The Boston AIA board needs a basic GbE NIC. There is no PCH GbE
device emulation, so use an `e1000e` instead. We place it in
**slot 0, function 1** in order not to conflict with the existing
AHCI device in slot 0 func 0.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw
-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/misc/Kconfig | 5 +
hw/misc/meson.build | 1 +
hw/misc/riscv_cpc.c | 239
include/hw/misc/riscv_cpc.h | 73 +++
4 files changed, 318 insertions(+)
create mode 100644 hw
Since there is no pch_gbe emulation, we could be using func other
than 0 when adding new devices to specific boards.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/pci/pci.c b
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
> On 3/7/25 12:49, Djordje Todorovic wrote:
>> The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
>> MIPS CPC, AIA plic, and AIA clint devices. The model can create
>> boot code, if there is no -bios parameter. We can specify -smp x,
>> cores=y,thread=z.
>
gt;
> On 3/7/25 12:49, Djordje Todorovic wrote:
>> Add RISC-V implementations of the Coherent Manager Global Control
>> Register (CMGCR) and Cluster Power Controller (CPC) devices. These
>> are based on the existing MIPS CMGCR and CPC implementations but
>> adapted for
Hi,
I am wondering if there is any comment on this.
Best regards,
Djordje
On 3. 7. 25. 12:49, Djordje Todorovic wrote:
> Since there is no pch_gbe emulation, we could be using func other
> than 0 when adding new devices to specific boards.
>
> Signed-off-by: Chao-ying Fu
>
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 3 +-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
Since there is no pch_gbe emulation, we could be using func other
than 0 when adding new devices to specific boards.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/pci/pci.c b
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/intc/riscv_aclint.c | 21
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 3 +
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 226 +++
4 files changed
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 15 +++
target/riscv/cpu_vendorid.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu-qom.h b
configurations, while the CPC device manages power control for
CPU clusters in RISC-V systems.
This is needed for the MIPS BOSTON AIA board.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/misc/Kconfig | 5 +
hw/misc/meson.build | 1 +
hw/misc
The Boston AIA board needs a basic GbE NIC. There is no PCH GbE
device emulation, so use an `e1000e` instead. We place it in
**slot 0, function 1** in order not to conflict with the existing
AHCI device in slot 0 func 0.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw
-system-riscv64 -cpu mips-p8700 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 13 +
target/riscv/cpu.h | 4
2 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu.c b/target
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 3 ++-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv
introduced a macro for 0x100 offset used in those features
The reset of the patches are the same.
Djordje Todorovic (11):
hw/intc: Allow gaps in hartids for aclint and aplic
target/riscv: Add cpu_set_exception_base
target/riscv: Add MIPS P8700 CPU
target/riscv: Add MIPS P8700 CSRs
target
click links or open attachments unless you recognize the sender
> and know the content is safe.
>
>
> On 6/18/25 9:27 AM, Djordje Todorovic wrote:
>> This is needed for riscv based CPUs by MIPS since those may have
>> sparse hart-ID layouts. ACLINT and APLIC still assume a de
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 15 +++
target/riscv/cpu_vendorid.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu-qom.h b
click links or open attachments unless you recognize the sender
> and know the content is safe.
>
>
> On 6/18/25 9:27 AM, Djordje Todorovic wrote:
>> Define MIPS CSRs used for P8700 CPU.
>>
>> Signed-off-by: Chao-ying Fu
>> Signed-off-by: Djordje Todorovic
>&g
om outside of the organization. Do
> not click links or open attachments unless you recognize the sender
> and know the content is safe.
>
>
> On 6/18/25 9:27 AM, Djordje Todorovic wrote:
>> The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
>> MIPS CPC, AI
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/intc/riscv_aclint.c | 21
Since there is no pch_gbe emulation, we could be using func other
than 0 when adding new devices to specific boards.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/pci/pci.c b
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 3 +
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 226 +++
4 files changed
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/misc/Kconfig
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.h | 4
target/riscv/translate.c | 8
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.h b
In v4 I am addressing review comments.
Djordje Todorovic (11):
hw/intc: Allow gaps in hartids for aclint and aplic
target/riscv: Add cpu_set_exception_base
target/riscv: Add MIPS P8700 CPU
target/riscv: Add MIPS P8700 CSRs
target/riscv: Add mips.ccmov instruction
target/riscv: Add
Ex: Use 4 cores and 2 threads with each core to
have 8 smp cpus as follows.
qemu-system-riscv64 -cpu mips-p8700 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 3 ++-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv
The Boston AIA board needs a basic GbE NIC. There is no PCH GbE
device emulation, so use an `e1000e` instead. We place it in
**slot 0, function 1** in order not to conflict with the existing
AHCI device in slot 0 func 0.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 3 +-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 14 ++
2 files changed, 15 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..1e62b96094
Several things implemented in v3:
- Addressing review comments
- Added documentation
- Referenced MIPS Specification
- Split e1000e and pci changes into separate patches
- Rebase on top of master branch
Djordje Todorovic (10):
hw/intc: Allow gaps in hartids for aclint and aplic
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 12 +++
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 219 +++
4 files changed
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 3 ++-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.h | 4
target/riscv/translate.c | 8
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.h b
-system-riscv64 -cpu mips-p8700 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv
The Boston AIA board needs a basic GbE NIC. There is no PCH GbE
device emulation, so use an `e1000e` instead. We place it in
**slot 0, function 1** in order not to conflict with the existing
AHCI device in slot 0 func 0.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
Since there is no pch_gbe emulation, we could be using func other
than 0 when adding new devices to specific boards.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/pci/pci.c b
This is needed for riscv based CPUs by MIPS since those may have
sparse hart-ID layouts. ACLINT and APLIC still assume a dense
range, and if a hart is missing, this causes NULL derefs.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/intc/riscv_aclint.c | 27
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 3 +-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
or open attachments unless you recognize the sender and know the
> content is safe.
>
>
> On Mon, Jun 2, 2025 at 11:13 PM Djordje Todorovic
> wrote:
>> Add mips.ccmov defined by Xmipscmov.
>>
>> Signed-off-by: Chao-ying Fu
>> Signed-off-by: Djordje Todorovic
On 10. 6. 25. 09:38, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do
> not click links or open attachments unless you recognize the sender
> and know the content is safe.
>
>
> Hi,
>
> On 2/6/25 15:12, Djordje Todor
On 10. 6. 25. 09:43, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do
> not click links or open attachments unless you recognize the sender
> and know the content is safe.
>
>
> On 2/6/25 15:12, Djordje Todorovic wrote:
>
On 10. 6. 25. 09:34, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do
> not click links or open attachments unless you recognize the sender
> and know the content is safe.
>
>
> Hi,
>
> On 2/6/25 15:12, Djordje Tod
or open attachments unless you recognize the sender and know the
> content is safe.
>
>
> On Mon, Jun 2, 2025 at 11:14 PM Djordje Todorovic
> wrote:
>> Several things implemented in v2:
>>- Addressing review comments
>> - Simplify `target/riscv/xmips.decod
Introduce MIPS P8700 CPU and set reset vector to 0x1fc0.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 16
2 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 3 +-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
This is needed for riscv based CPUs by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/intc/riscv_aclint.c | 33 +++--
hw/intc/riscv_aplic.c | 10 +++---
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/hw/intc
Add a new function, so we can change reset vector from platforms.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.h | 2 ++
target/riscv/translate.c | 8
2 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 7 ++
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 219 +++
4 files changed
-system-riscv64 -cpu mips-p8700,resetvec=0x1fc0 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
configs/devices/riscv64-softmmu/default.mak | 1
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 3 ++-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv
Add a network device e1000e to the boston-aia board model.
There is no pch_gbe emulation, so we add e1000e in slot 0 func 1,
instead. We need to pass func to call pci_parse_devaddr to find
out slot and func.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 5 +++
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans
Several things implemented in v2:
- Addressing review comments
- Simplify `target/riscv/xmips.decode`
- Rebase on top of latest master
- Fix code format
Djordje Todorovic (9):
hw/intc: Allow gaps in hartids for aclint and aplic
target/riscv: Add cpu_set_exception_base
target/riscv
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 ++
target/riscv/cpu_cfg.h| 6
target/riscv/insn_trans/trans_xmips.c.inc | 38 +++
target/riscv
Add a new function, so we can change reset vector from platforms.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.h | 1 +
target/riscv/translate.c | 8
2 files changed, 9 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +
target/riscv/cpu_cfg.h| 3 +-
target/riscv/insn_trans/trans_xmips.c.inc | 84 +++
target
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 3 ++-
target/riscv/insn_trans/trans_xmips.c.inc | 14
This is needed for riscv based CPUs by MIPS.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/intc/riscv_aclint.c | 24 ++--
hw/intc/riscv_aplic.c | 9 ++---
2 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 7 ++
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 226 +++
4 files changed
ucing enhancements that set it apart. For more details,
you can check out the official product page here:
https://mips.com/products/hardware/p8700/.
Djordje Todorovic (9):
hw/intc: Allow gaps in hartids for aclint and aplic
target/riscv: Add cpu_set_exception_base
target/riscv: Add MIPS P870
Add a network device e1000e to the boston-aia board model.
There is no pch_gbe emulation, so we add e1000e in slot 0 func 1,
instead. We need to pass func to call pci_parse_devaddr to find
out slot and func.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
hw/pci/pci.c
-system-riscv64 -cpu mips-p8700 -m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
configs/devices/riscv64-softmmu/default.mak | 1 +
hw/misc/Kconfig
Introduce MIPS P8700 CPU and set reset vector to 0x1fc0.
Signed-off-by: Chao-ying Fu
Signed-off-by: Djordje Todorovic
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 29 +
2 files changed, 30 insertions(+)
diff --git a/target/riscv/cpu-qom.h b
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