On 10. 6. 25. 09:38, Philippe Mathieu-Daudé wrote:
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>
> Hi,
>
> On 2/6/25 15:12, Djordje Todorovic wrote:
>> Introduce MIPS P8700 CPU and set reset vector to 0x1fc00000.
>>
>> Signed-off-by: Chao-ying Fu <c...@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
>> ---
>> target/riscv/cpu-qom.h | 1 +
>> target/riscv/cpu.c | 16 ++++++++++++++++
>> 2 files changed, 17 insertions(+)
>>
>> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
>> index 1ee05eb393..1e62b96094 100644
>> --- a/target/riscv/cpu-qom.h
>> +++ b/target/riscv/cpu-qom.h
>> @@ -55,6 +55,7 @@
>> #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
>> #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
>> #define TYPE_RISCV_CPU_XIANGSHAN_NANHU
>> RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
>> +#define TYPE_RISCV_CPU_MIPS_P8700 RISCV_CPU_TYPE_NAME("mips-p8700")
>> #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
>>
>> OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 629ac37501..519d2345b8 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -3167,6 +3167,22 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>> .cfg.max_satp_mode = VM_1_10_SV39,
>> ),
>>
>> + // NOTE: When specifying CPU, specify `resetvec` as:
>> + // -cpu mips-p8700,resetvec=0x1fc00000
>
> Do you think users will go read the code for comments before using QEMU?
> (please respect QEMU coding style).
>
> Maybe resetvec has to be added to RISCVCPUProfile?
>
This is not needed and the comment should be removed.
Anyway, we will add the documentation file for the MIPS CPUs as proposed
in another patch review.
Thanks a lot!
>> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU,
>> + .misa_mxl_max = MXL_RV64,
>> + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
>> + .priv_spec = PRIV_VERSION_1_12_0,
>> + .cfg.max_satp_mode = VM_1_10_SV48,
>> + .cfg.ext_zifencei = true,
>> + .cfg.ext_zicsr = true,
>> + .cfg.mmu = true,
>> + .cfg.pmp = true,
>> + .cfg.ext_zba = true,
>> + .cfg.ext_zbb = true,
>> + .cfg.marchid = 0x8000000000000201,
>> + ),
>> +
>> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
>> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
>> .cfg.max_satp_mode = VM_1_10_SV57,
>
