Several things implemented in v3:
- Addressing review comments
- Added documentation
- Referenced MIPS Specification
- Split e1000e and pci changes into separate patches
- Rebase on top of master branch
Djordje Todorovic (10):
hw/intc: Allow gaps in hartids for aclint and aplic
target/riscv: Add cpu_set_exception_base
target/riscv: Add MIPS P8700 CPU
target/riscv: Add MIPS P8700 CSRs
target/riscv: Add mips.ccmov instruction
target/riscv: Add mips.pref instruction
target/riscv: Add Xmipslsp instructions
configs/devices: Add MIPS Boston-aia board model to RISC-V
hw/pci: Allow explicit function numbers in pci
riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv/mips.rst | 25 +
docs/system/target-riscv.rst | 1 +
hw/intc/riscv_aclint.c | 27 +-
hw/intc/riscv_aplic.c | 10 +-
hw/misc/Kconfig | 5 +
hw/misc/meson.build | 1 +
hw/misc/riscv_cmgcr.c | 206 +++++++++
hw/misc/riscv_cpc.c | 225 +++++++++
hw/pci/pci.c | 15 +-
hw/riscv/Kconfig | 6 +
hw/riscv/boston-aia.c | 489 ++++++++++++++++++++
hw/riscv/cps.c | 187 ++++++++
hw/riscv/meson.build | 1 +
include/hw/misc/riscv_cmgcr.h | 77 +++
include/hw/misc/riscv_cpc.h | 69 +++
include/hw/riscv/cps.h | 75 +++
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 26 ++
target/riscv/cpu.h | 16 +
target/riscv/cpu_cfg.h | 5 +
target/riscv/cpu_cfg_fields.h.inc | 3 +
target/riscv/insn_trans/trans_xmips.c.inc | 140 ++++++
target/riscv/meson.build | 2 +
target/riscv/mips_csr.c | 219 +++++++++
target/riscv/translate.c | 11 +
target/riscv/xmips.decode | 35 ++
27 files changed, 1867 insertions(+), 11 deletions(-)
create mode 100644 docs/system/riscv/mips.rst
create mode 100644 hw/misc/riscv_cmgcr.c
create mode 100644 hw/misc/riscv_cpc.c
create mode 100644 hw/riscv/boston-aia.c
create mode 100644 hw/riscv/cps.c
create mode 100644 include/hw/misc/riscv_cmgcr.h
create mode 100644 include/hw/misc/riscv_cpc.h
create mode 100644 include/hw/riscv/cps.h
create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
create mode 100644 target/riscv/mips_csr.c
create mode 100644 target/riscv/xmips.decode
--
2.34.1
