issue by moving the guard check earlier,
> preventing the problematic wraparound when pmpaddrX is zero.
>
> Signed-off-by: Vac Chen
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/pmp.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
&g
issue by moving the guard check earlier,
> preventing the problematic wraparound when pmpaddrX is zero.
>
> Signed-off-by: Vac Chen
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmp.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --g
upported together with C and F extension
```
Alistair
>
> lxx (1):
> target/riscv: Add Zilsd and Zclsd extension support
>
> target/riscv/cpu.c| 4 +
> target/riscv/cpu_cfg_fields.h.inc | 2 +
> target/riscv/insn16.decode
On Wed, Jul 2, 2025 at 5:31 PM Alexandre Ghiti wrote:
>
> The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
> for software to use.
>
> Reviewed-by: Deepak Gupta
> Signed-off-by: Alexandre Ghiti
Thanks!
Applied to riscv-to-apply.next
Alistair
>
other
> archs.
>
> Cc: Dr. David Alan Gilbert
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> monitor/hmp-cmds-target.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/monitor/hmp-cmds-target.c b
kovitis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/riscv/helper.h | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
> target/ri
.net/wiki/spaces/HOME/pages/16154882/All+RISC-V+Specifications+Under+Active+Development
>
> Signed-off-by: Roan Richmond
> ---
>
> Ping! resending this as no movement on previous send.
>
> V3:
> - rebased patch onto master branch
> - added check for aq on Load Acquire
.net/wiki/spaces/HOME/pages/16154882/All+RISC-V+Specifications+Under+Active+Development
>
> Signed-off-by: Roan Richmond
Reviewed-by: Alistair Francis
Alistair
> ---
>
> Ping! resending this as no movement on previous send.
>
> V3:
> - rebased patch onto master branch
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.c| 4 +
> target/riscv/cpu_cfg_fields.h.inc | 2 +
> target/riscv/insn16.decode| 8 ++
> target/riscv/insn32.decode| 12
re
> written to MEPC and not properly cleared, causing incorrect behavior
> on MRET.
>
> Charalampos Mitrodimas (2):
> target/riscv: Fix MEPC/SEPC bit masking for IALIGN
> tests/tcg/riscv64: Add test for MEPC bit masking
Thanks!
Applied to riscv-to-apply.next
, when vectored mode bits from STVEC (which sets bit 0 for
> vectored mode) were written to MEPC, the bits would not be cleared
> correctly, causing incorrect behavior on MRET.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2855
> Signed-off-by: Charalampos Mi
support KVM AIA")
>
> Signed-off-by: Xuemei Liu
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Changes in v3:
> - Increase version_id and minimum_version_id
>
> hw/intc/riscv_aplic.c | 12 ++--
> hw/intc/riscv_imsic.c | 10 --
>
to migration failure
> characterized by uninitialized fields when save vm state:
> qemu-system-riscv64: ../migration/vmstate.c:433: vmstate_save_state_v:
> Assertion 'first_elem || !n_elems || !size' failed.
>
> Fixes: 95a97b3fd2 ("target/riscv: update APLIC an
On Tue, Jun 24, 2025 at 1:12 PM Jay Chang wrote:
>
> Hi,
>
> Gentle ping on this patch.
Sorry it slipped through. Can you include a cover letter to makes
things easier to manage [1]
1:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#include-a-meaningful-cover-lett
ction to
> make sure the vl_eq_vlmax TB flag is correct.
>
> Signed-off-by: Max Chou
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans
On Fri, Apr 25, 2025 at 10:18 PM Ran Wang wrote:
>
> This serial adds Xiangshan Kunminghu CPU and its FPGA prototype
> platform, which include UART, CLINT, IMSIC, and APLIC
> devices.
>
> More details can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Patc
by: SUN Dongya
> Co-developed-by: ZHAO Fujin
> Reviewed-by: Alistair Francis
This breaks with linux-user (which is using the "max" CPU)
./build/qemu-riscv64 ./images/qemuriscv64/target-rootfs/usr/bin/sha512sum ...
qemu-riscv64: Zclsd cannot be supported together with C and F ex
init’)
../hw/riscv/xiangshan_kmh.c:134:13: note:
‘xiangshan_kmh_soc_class_init’ declared here
134 | static void xiangshan_kmh_soc_class_init(ObjectClass *klass, void *data)
| ^~~~
../hw/riscv/xiangshan_kmh.c:213:19: error: initialization of ‘void
(*)(Obj
by: SUN Dongya
> Co-developed-by: ZHAO Fujin
> Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c| 4 +
> target/riscv/cpu_cfg_fields.h.inc | 2 +
> target/riscv/insn16.decode
le with `!function=ex_rvc_register`.
You are right!
In future please reply inline and in plain text though.
This is good to go then, do you mind rebasing it on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
sending a v8
Alistair
>
> Alistair Francis 在 2025年6月11日 周三 12:47 写道：
> On T
On Wed, Jun 4, 2025 at 12:58 PM Joel Stanley wrote:
>
> v2:
> - Rebased on master now that Daniel's changes are merged
> - Fixed doubled up patch 1
> - r-b tags from Alistair and Daniel added
>
> This is a set of cleanups for the riscv virt machine device tree
>
On Wed, Jun 11, 2025 at 7:33 PM Roan Richmond
wrote:
>
>
> On 11/06/2025 05:29, Alistair Francis wrote:
> > On Tue, Jun 10, 2025 at 6:33 PM Roan Richmond
> > wrote:
> >> This is based on version v0.8.3 of the ZALASR specification [1].
> >> The specif
isasContext *ctx, arg_sd *a)
> +{
> +if ((a->rs2) % 2) {
> +return false;
> + }
> +
> +TCGv data_low = get_gpr(ctx, a->rs2, EXT_NONE);
> +TCGv data_high = get_gpr(ctx, a->rs2 + 1, EXT_NONE);
> +TCGv addr = get_address(ctx, a->rs1, a->imm);
>
On Tue, Jun 10, 2025 at 6:33 PM Roan Richmond
wrote:
>
> Ping, resending as no responses in over week.
>
> V2:
> - rebased patch onto master branch
> - added check for RV64() for Load Double, as pointed out by Alistair Palmer.
>
> In response to Alistair Palmer
ntext *ctx, arg_lw_aqrl *a)
> +{
> +REQUIRE_ZALASR(ctx);
> +return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
> +{
> +REQUIRE_64BIT(ctx);
> + REQUIRE_ZALASR(ctx);
> +return gen_
sp instructions
> configs/devices: Add MIPS Boston-aia board model to RISC-V
> hw/riscv: Add a network device e1000e to the boston-aia
Thanks for the patches! There are now some review comments (sorry for
the delay), please send a v3 once they have been addressed
Alistair
>
>
device address %s for device %s",
> devaddr, model);
> exit(1);
> @@ -2062,7 +2065,7 @@ bool pci_init_nic_in_slot(PCIBus *rootbus, const char
> *model,
> exit(1);
> }
>
> -devfn = PCI_DEVFN(slot, 0);
> +devfn = PC
ext_xtheadmemidx)
> BOOL_FIELD(ext_xtheadmempair)
> BOOL_FIELD(ext_xtheadsync)
> BOOL_FIELD(ext_XVentanaCondOps)
> +BOOL_FIELD(ext_xmipscmov)
>
> BOOL_FIELD(mmu)
> BOOL_FIELD(pmp)
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc
> b/target/riscv/insn_trans
ot helpful at all).
>
> Alternatively:
>
> struct {
> uint64_t tvec;
> uint64_t config[12];
> uint64_t pmacfg[15];
> } mips;
We don't want to store these in the CPUArchState. So you will need to
create a vendor specific struct and you can then point to that from
CPUArchState, similar to the existing `RISCVCSR *custom_csrs`
Alistair
>
> > };
>
>
v/sifive_u.c for examples
Alistair
>
> Signed-off-by: Chao-ying Fu
> Signed-off-by: Djordje Todorovic
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/translate.c | 8
> 2 files changed, 10 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/
On Mon, Jun 9, 2025 at 11:18 PM Ben Dooks wrote:
>
> Add TYPE_RISCV_CPU_CVA6 for the CVA6 core
>
> Signed-off-by: Ben Dooks
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 11 +++
> 2 files changed, 1
On Mon, Jun 9, 2025 at 11:20 PM Ben Dooks wrote:
>
> Change to using TYPE_RISCV_CPU_CVA6 once this is merged.
You can also just change the patch order to not require this patch
>
> Signed-off-by: Ben Dooks
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/riscv/cva6.c
+memmap[CVA6_PLIC].size);
> +
> +riscv_aclint_swi_create(memmap[CVA6_CLINT].base, 0,
> +ms->smp.cpus, false);
> +
> +riscv_aclint_mtimer_create(
> +memmap[CVA6_CLINT].base + RISCV_ACLINT_SWI_SIZE,
> +RISCV_ACLINT_D
being infinitly pushed back.
>
> This commit fixes the issue by never pushing back the timer, only
> updating it if it is not already active.
>
> Signed-off-by: Florian Lugou
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/char/sifive_uart.c | 6 --
being infinitly pushed back.
You would hope the guest software doesn't write to the register when
the FIFO is full
>
> This commit fixes the issue by never pushing back the timer, only
> updating it if it is not already active.
The fix looks correct though
>
> Signed-off-by
On Thu, May 1, 2025 at 9:44 PM Anton Blanchard wrote:
>
> fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16
> quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN.
>
> Signed-off-by: Anton Blanchard
Thanks!
Applied to riscv-to-apply.next
Alistair
On Thu, May 1, 2025 at 9:44 PM Anton Blanchard wrote:
>
> fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16
> quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN.
>
> Signed-off-by: Anton Blanchard
Acked-by: Alistair Francis
Alistair
> -
can be found at
> https://github.com/OpenXiangShan/XiangShan
>
> Signed-off-by: qinshaoqing
> Signed-off-by: Yang Wang
> Signed-off-by: Yu Hu
> Signed-off-by: Ran Wang
> Signed-off-by: Borong Huang <3543977...@qq.com>
> Reviewed-by: Daniel Henrique Barboza
Acked
rnel.org/qemu-riscv/416e68f4-bf12-4218-ae2d-0246cc8ea...@linaro.org/T/#u
>
> --
> Regards,
> Chao
>
> Chao Liu (1):
> hw/riscv: fix PLIC hart topology configuration string when not getting
> CPUState correctly
>
> hw/intc/sifive_plic.c | 4 ++--
> hw/riscv/boot.c| 4 ++--
> hw/riscv/microchip_pfsoc.c | 2 +-
> hw/riscv/sifive_u.c| 2 +-
> hw/riscv/virt.c| 2 +-
> include/hw/riscv/boot.h| 2 +-
> 6 files changed, 8 insertions(+), 8 deletions(-)
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> --
> 2.49.0
>
mu_get_cpu(),
> in riscv cpu_by_arch_id() uses the mhartid.
>
> For non-numa or single-cluster machines, hartid_base should be 0.
>
> Signed-off-by: Chao Liu
> Reviewed-by: Tingjian Zhang
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/intc/sifive_plic.c | 4 ++--
&g
anamicro.com/
>
> Daniel Henrique Barboza (1):
> target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/kvm/kvm-cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> --
> 2.49.0
>
>
> or used until now, so just remove the definitions. They can be added
> back when really necessary.
>
> Signed-off-by: Zhenzhong Duan
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> include/hw/riscv/iommu.h | 6 ++
> hw/riscv
y in the PPN field of
> Translation-reponse register.
>
> Also remove the code that was used to clear S field since this
> field is already zero.
>
> Signed-off-by: Nutty Liu
> Reviewed-by: Tomasz Jeznach
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> V1 ->
-by: Jay Chang
> Reviewed-by: Frank Chang
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c| 48 +--
> target/riscv/cpu.h| 3 +-
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/ri
-by: Jay Chang
> Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 48 +--
> target/riscv/cpu.h| 3 +-
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/riscv/csr.c
uo
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Change in v6:
> - Rebase on https://github.com/alistair23/qemu/tree/riscv-to-apply.next
> - Minor change in title
>
> Change in v5:
> - Adds R-B comment from Andrew Jones
>
> Change in v4:
> - Add
On Thu, Jun 5, 2025 at 3:34 PM Jay Chang wrote:
>
> Hi Daniel,
>
> You're absolutely right — thanks for pointing it out and providing the fix!
>
> Would you like me to send out a v5 patch incorporating your changes?
Yes please
Alistair
>
>
> Best Regards
>
wants to provide this feature by HW. RVA20U64
> Ziccif protects the atomicity of instruction fetch when it is
> natural aligned.
>
> This commit depends on the atomic read support of translator_ld in
> the commit 6a9dfe1984b0c593fb0ddb52d4e70832e6201dd6.
>
> Signed-off-by: Jim Shu
&g
wants to provide this feature by HW. RVA20U64
> Ziccif protects the atomicity of instruction fetch when it is
> natural aligned.
>
> This commit depends on the atomic read support of translator_ld in
> the commit 6a9dfe1984b0c593fb0ddb52d4e70832e6201dd6.
>
> Signed-off-by: Ji
et/riscv: add 'rva22u64' CPU")
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
> Reviewed-by: Björn Töpel
> Tested-by: Björn Töpel
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 127 +++-
> Signed-off-by: Daniel Henrique Barboza
> Message-ID: <20250529202315.1684198-4-dbarb...@ventanamicro.com>
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/targe
* cpu.debug = true is marked as 'sdtrig', priv spec 1.12.
> + * Skip this warning dince existing CPUs with older priv
since
> + * specd and debug = true will be impacted.
spec
Otherwise:
Reviewed-by: Alistair Francis
Alistair
> + */
> +if
REQUIRE_ZALASR(ctx);
There should be a RV64 check here
> +return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));
> +}
> +
> +static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> +{
> +decode_save_opc(ctx, 0);
> +
> +TCGv addr = ge
e chapter
> order in the specifications.
>
> Signed-off-by: Yu Hu
> Signed-off-by: Ran Wang
> Signed-off-by: Borong Huang <3543977...@qq.com>
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> tar
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cd0b159ed5..fdf2eb2b1c 10064
gt;
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9d6fae72b2..cd0b159ed5 100644
> --- a/target/
mu_get_cpu(),
> in riscv cpu_by_arch_id() uses the mhartid.
>
> For non-numa or single-cluster machines, hartid_base should be 0.
>
> Signed-off-by: Chao Liu
> Reviewed-by: Tingjian Zhang
> Reviewed-by: Alistair Francis
Should be:
Reviewed-by: Alistair Francis
Otherw
On Fri, May 30, 2025 at 6:24 AM Daniel Henrique Barboza
wrote:
>
> We have support for sdtrig for awhile but we are not advertising it. It
> is enabled by default via the 'debug' flag. Use the same flag to also
> advertise sdtrig.
>
> Signed-off-by: Daniel Henrique Bar
s the same as
iova >> TARGET_PAGE_BITS
and
set_field(0, RISCV_IOMMU_TR_RESPONSE_PPN, PPN_DOWN(iova))
should just return
(0 & ~RISCV_IOMMU_TR_RESPONSE_PPN) |
(RISCV_IOMMU_TR_RESPONSE_PPN & PPN_DOWN(iova))
Can you describe the issue with the original implementation and why
e
> 'sdext'. I guess we'll have to postpone the Server Soc Ref work for now.
>
> Daniel Henrique Barboza (3):
> target/riscv/cpu.c: add 'sdtrig' in riscv,isa
> target/riscv/cpu.c: add 'ssstrict' to riscv,isa
> target/riscv/cpu.c: do bett
satp_mode, bool
> is_32_bit)
> g_assert_not_reached();
> }
>
> -static void set_satp_mode_max_supported(RISCVCPU *cpu,
> -uint8_t satp_mode)
> +void set_satp_mode_max_supported(RISCVCPU *cpu, uint8_t satp_mode)
> {
This function has been removed in the latest mast
On Fri, May 30, 2025 at 11:47 PM Daniel Henrique Barboza
wrote:
>
> These properties were deprecated in QEMU 8.2, commit 8043effd9b.
>
> Signed-off-by: Daniel Henrique Barboza
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 17 -
On Fri, May 30, 2025 at 11:47 PM Daniel Henrique Barboza
wrote:
>
> These properties were deprecated in QEMU 8.2, commit 8043effd9b.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 17 ---
:
> * Changed `pmp_regions` type from `uint16_t` to `uint8_t`
> * Introduced `OLD_MAX_RISCV_PMPS` macro
>
> Jay Chang (2):
> target/riscv: Extend PMP region up to 64
> target/riscv: Make PMP region count configurable
Thanks!
Applied to riscv-to-apply.nex
-by: Jay Chang
> Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 54 +--
> target/riscv/cpu.h| 3 +-
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/riscv/csr.c
user prop
> target/riscv: add profile->present flag
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h| 15
> target/riscv/riscv-qmp-cmds.c | 2 +-
> target/riscv/tcg/tcg-cpu.c| 138 +-
> 3 files changed, 86 insertions(+), 69 deletions(-)
>
> --
> 2.49.0
>
>
>
> [1]
> https://lore.kernel.org/qemu-riscv/87y0usiz22@all.your.base.are.belong.to.us/
>
> Reported-by: Björn Töpel
> Fixes: 2af005d610 ("target/riscv/tcg: validate profiles during finalize")
> Signed-off-by: Daniel Henrique Barboza
>
> Signed-off-by: Daniel
On Wed, May 28, 2025 at 4:13 PM Ethan Chen wrote:
>
> On Thu, May 22, 2025 at 11:24:28AM +1000, Alistair Francis wrote:
> > [EXTERNAL MAIL]
> >
> > On Wed, Mar 12, 2025 at 7:43 PM Ethan Chen via
> > wrote:
> > >
> > > - Add 'iopmp=o
et/riscv: add 'rva22u64' CPU")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 127 +++--
> 1 file changed, 67 insertions(+), 60 deletions(-)
>
> diff --g
ituation where we'll set mmu=on without a virtual
> memory mode, which is a mistake.
>
> Only touch 'mmu' and satp_mode if the profile is being enabled.
>
> Suggested-by: Andrew Jones
> Fixes: 55398025e7 ("target/riscv: add satp_mode profile support")
On Thu, May 22, 2025 at 9:35 PM Daniel Henrique Barboza
wrote:
>
> Put it after zalrsc and before zawrs.
>
> Cc: qemu-triv...@nongnu.org
> Fixes: a60ce58fd9 ("target/riscv: Support Zama16b extension")
> Signed-off-by: Daniel Henrique Barboza
Thanks!
Applied to r
On Thu, May 22, 2025 at 9:35 PM Daniel Henrique Barboza
wrote:
>
> Put it after zalrsc and before zawrs.
>
> Cc: qemu-triv...@nongnu.org
> Fixes: a60ce58fd9 ("target/riscv: Support Zama16b extension")
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by:
mu_get_cpu(),
> in riscv cpu_by_arch_id() uses the mhartid.
>
> For non-numa or single-cluster machines, hartid_base should be 0.
>
> Signed-off-by: Chao Liu
> Reviewed-by: Qingze Zhao
> Reviewed-by: Tingjian Zhang
Do you mind rebasing this on
https://github.com/alistair23/
mu_get_cpu(),
> in riscv cpu_by_arch_id() uses the mhartid.
>
> For non-numa or single-cluster machines, hartid_base should be 0.
>
> Signed-off-by: Chao Liu
> Reviewed-by: Qingze Zhao
> Reviewed-by: Tingjian Zhang
Reviewed-by: Alistair Francis
Alistair
> ---
> hw
ions when errors are suppressed)
> +- msi_en: false (Options: true/false)
> +- msidata: 12 (Range: 1-1023)
> +- stall_violation_en: true (Options: true/false)
> +- err_msiaddr: 0x2400 (lower-part 32-bit address)
> +- err_msiaddrh: 0x0 (higher-part 32-bit address)
> +- msi_rrid
version of a draft spec
1:
https://patchew.org/QEMU/20250122083617.3940240-1-etha...@andestech.com/20250122084655.3968598-1-etha...@andestech.com/
Alistair
>
> The IOPMP checks whether memory access from a device or CPU is valid.
> This implementation uses an IOMMU to modify the address sp
t;
> Signed-off-by: Ethan Chen
Acked-by: Alistair Francis
Alistair
> ---
> include/hw/misc/riscv_iopmp_txn_info.h | 38 ++
> 1 file changed, 38 insertions(+)
> create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
>
> diff --git a/include/hw/m
419..d80eb1eb7b 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -163,6 +163,7 @@ TYPED_FIELD(uint16_t, elen, 0)
> TYPED_FIELD(uint16_t, cbom_blocksize, 0)
> TYPED_FIELD(uint16_t, cbop_blocksize, 0)
> TYPED_FIELD(uint16_t, cboz_blocksize,
On Fri, Apr 25, 2025 at 7:45 PM Jay Chang wrote:
>
> According to the RISC-V Privileged Specification (version >1.12),
> RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions
> (pmpaddr0–pmpaddr63).
>
> Reviewed-by: Frank Chang
> Signed-off-by: Jay Chang
On Tue, May 20, 2025 at 3:08 PM Michael Tokarev wrote:
>
> On 19.05.2025 07:04, alistai...@gmail.com wrote:
> > From: Alistair Francis
>
> > First RISC-V PR for 10.1
> >
> > * Add support for RIMT to virt machine ACPI
> > * Don't allow PMP RLB to bypas
de Timer when STCE bit is changed
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/intc/riscv_aclint.c | 5 +++
> target/riscv/csr.c | 55 +++-
> target/riscv/time_helper.c | 65 --
> target
23/qemu/tree/riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 3 +--
> target/riscv/cpu.h | 1 +
> target/riscv/kvm/kvm-cpu.c | 20 +++-
> 3 files changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c
> target/riscv: Fix VSTIP bit in sstc extension.
> target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
Can you please rebase this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Alistair
>
> hw/intc/riscv_aclin
On Wed, Apr 9, 2025 at 12:52 PM Jim Shu wrote:
>
> Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
> also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR.
>
> Signed-off-by: Jim Shu
Acked-by: Alistair Francis
Alistair
> ---
>
On Mon, Apr 28, 2025 at 6:57 PM Meng Zhuo wrote:
>
> This patch adds host satp mode while kvm/host cpu satp mode is not
> set.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
> Signed-off-by: Meng Zhuo
Reviewed-by: Alistair Francis
Alistair
> ---
register, whenever (time + htimedelta),
> truncated to 64 bits, contains a value greater than or equal to
> vstimecmp
>
> Signed-off-by: Jim Shu
Acked-by: Alistair Francis
Alistair
> ---
> hw/intc/riscv_aclint.c | 5 +
> 1 file changed, 5 insertions(+)
>
ic->msimode);
> +}
> +
> static const VMStateDescription vmstate_riscv_aplic = {
> .name = "riscv_aplic",
> .version_id = 2,
> .minimum_version_id = 2,
I think these should also be incremented
Alistair
> +.needed = riscv_aplic_state_needed,
On Tue, May 6, 2025 at 8:47 AM Daniel Henrique Barboza
wrote:
>
> Hi Alistair,
>
>
> I think we should push this upstream and see what happens. We'll have a
> full release cycle to undo the change in case we find unintended side
> effects. I'm fairly optimistic t
Reviewed-by: Jerry Zhang Jian
> Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 27edd5af62..f737b703
On Mon, May 5, 2025 at 6:59 AM Richard Henderson
wrote:
>
> Check 32 vs 64-bit and pointer masking state.
>
> Cc: qemu-ri...@nongnu.org
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 26 +++
On Mon, May 12, 2025 at 7:53 PM Paolo Bonzini wrote:
>
> Start putting all the CPU definitions in a struct. Later this will replace
> instance_init functions with declarative code, for now just remove the
> ugly cast of class_data.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by
> target/riscv: remove .instance_post_init
> qom: reverse order of instance_post_init calls
This doesn't seem to have made it through to Patchew for some reason:
https://patchew.org/search?q=SATP+mode+and+CPU+definition+overhaul
Alistair
>
> include/qom/object.h
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 75 ++
> 1 file changed, 35 insertions(+), 40 deletions(-)
>
> diff
ll registration of properties to .instance_init,
> call accel_cpu_instance_init() at the end of riscv_cpu_init().
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
&
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 80 +-
> 1 file changed, 23 insertions(+), 57 deletions(-)
>
> diff
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 127 +
> 1 file changed, 60 insertions(+), 67 deletions(-)
>
> diff
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 61 +-
> 1 file changed, 28 insertions(+), 33 deletions(-)
>
> diff
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> While at it, constify it so that the RISCVCSR array in RISCVCPUDef
> can also be const.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h| 15 ---
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> In preparation for generalizing the custom CSR functionality,
> make the test return bool instead of int. Make the insertion_test
> optional, too.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistai
On Mon, May 12, 2025 at 7:54 PM Paolo Bonzini wrote:
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 79 +++---
> 2 files changed, 37 insertion
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