Hi,
> +uhci_devname[sizeof(uhci_devname) - 2] = ((char)'1') + i;
snprintf(devname, sizeof(devname), "...%d", i) is more readable.
> +qdev_prop_set_string(usb_qdev, "masterbus", "ich9-usb-bus.0");
Any reason why you rename the usb bus?
cheers,
Gerd
From: Igor Mitsyanko
Custom Exynos4210 SD/MMC host controller, based on SD association standard host
controller ver. 2.00.
Signed-off-by: Igor Mitsyanko
Signed-off-by: Peter Crosthwaite
---
Hi Igor,
I had to change this patch significantly without any testing so I dont have any
confidence in
The Xilinx Zynq device has two SDHCI controllers. Added to the machine model.
Reviewed-by: Peter Maydell
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_zynq.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index c55dafb..3
Allows for repeating of -sd arguments in the same way as -pflash and -mtdblock.
Acked-by: Igor Mitsyanko
Reviewed-by: Peter Maydell
Signed-off-by: Peter Crosthwaite
---
vl.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/vl.c b/vl.c
index 5a3d316..978bd68 100644
---
[Original cover by Igor]
First patch introduces standard SD host controller model. This is accumulated
version of my previous patch I sent a while ago and a recent SDHCI patch by
Peter A. G. Crosthwaite. Second patch introduces Exynos4210-specific SDHCI
built on top of standard SDHCI model.
Sec
I've found that git status of my local repo is somewhat twisted.
Sorry for your inconvenience. I'll send new patch after cleaning my repo.
On 2012년 10월 29일 23:32, Yeongkyoon Lee wrote:
Here is the 7th version of the series optimizing TCG qemu_ld/st code generation.
v7:
- Rebase and fix misty
On 10/29/2012 01:45 AM, Paolo Bonzini wrote:
Il 26/10/2012 22:29, H. Peter Anvin ha scritto:
This is surreal. Output from /dev/hwrng turns into output for /dev/random...
it us guaranteed worse; period, end of story.
Isn't that exactly what happens in bare-metal? hwrng -> rngd -> random.
In
Hi Cam,
Does nahanni support asynchronous communication between multi-guests in
the same machine? Besides, is the Nahanni-MPI latency in your slide
"Nahanni: a shared memory interface for KVM" the average result or the
maximal result?
Thanks,
Yi
On 10/29/2012 01:45 AM, Paolo Bonzini wrote:
First, hwrng is only one of the sources used by rngd. It can also
(currently) use RDRAND or TPM; additional sources are likely to be added
in the future.
Second, the harvesting of environmental noise -- timings -- is not as
good in a VM as on plain h
On 10/28/2012 11:23 PM, Amit Shah wrote:
One solution could be to feed host's /dev/urandom to readers of
guests' /dev/urandom. We could then pass the rare true entropy bits
from host's /dev/hwrng or /dev/random to the guest via
virtio-rng-pci's /dev/hwrng interface in the guest.
If this is a va
From: Ben Herrenschmidt
Kernel-based RTAS calls will not have a qemu handler, but will
still be registered in qemu in order to be assigned a token
number and appear in the device-tree.
Let's test for the name being NULL rather than the handler
when deciding to skip an entry while building the de
Throughout xics.c 'nr' is used to refer to a global interrupt number, and
'server' is used to refer to an interrupt server number (i.e. CPU number).
Except in icp_set_mfrr(), where 'nr' is used as a server number. Fix this
confusing inconsistency.
Signed-off-by: David Gibson
---
hw/xics.c |
From: Alexey Kardashevskiy
In future (with VFIO) we will have multiple PCI host bridges on
pseries. Each one needs a unique LIOBN (IOMMU id). At the moment we
derive these from the pci domain number, but the whole notion of
domain numbers on the qemu side is bogus and in any case they're not
ac
A couple of places in xics.c open-coded the same logic as is already
implemented in ics_valid_irq(). This patch fixes the code duplication.
Signed-off-by: David Gibson
---
hw/xics.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/xics.c b/hw/xics.c
index db01fe3.
Currently the ppcemb_tlb_t struct, used on a number of embedded ppc models
to represent a TLB entry contains a hwaddr. That works reasonably for now,
but is troublesome for saving the state, which we'll want to do in future.
hwaddr is a large enough type to contain a physical address for any
suppo
The PAPR specification requires a certain amount of NVRAM, accessed via
RTAS, which we don't currently implement in qemu. This patch addresses
this deficiency, implementing the NVRAM as a VIO device, with some glue to
instantiate it automatically based on a machine option.
The machine option spec
This reverts commit a178274efabcbbc5d44805b51def874e47051325.
Contrary to that commit's message, the users of old_portio are not all
gone. In particular VGA still uses it via portio_list_add().
Signed-off-by: David Gibson
---
hw/spapr_pci.c | 44 +++-
This patch adds some extra FPU state to CPUPPCState. Specifically,
fpscr is extended to a target_ulong bits, since some recent (64 bit)
CPUs now have more status bits than fit inside 32 bits. Also, we add
the 32 VSR registers present on CPUs with VSX (these extend the
standard FP regs, which toge
From: Ben Herrenschmidt
Currently, the pseries machine initializes the cpus, then the XICS
interrupt controller. However, to support the upcoming in-kernel XICS
implementation we will need to initialize the irq controller before the
vcpus. This patch makes the necesssary rearrangement. This me
From: Alexey Kardashevskiy
In one of the recent reworks to the XICS code, a bug was introduced where
we use the wrong sense and allocate level interrupts instead of message
interrupts for PCI MSIs. This patch fixes it.
Signed-off-by: Alexey Kardashevskiy
Signed-off-by: David Gibson
---
hw/sp
This patch adds tracing / debugging calls to the XICS interrupt controller
implementation used on the pseries machine.
Signed-off-by: Ben Herrenschmidt
Signed-off-by: David Gibson
---
hw/xics.c| 23 ---
trace-events | 13 +
2 files changed, 33 insertions(
With PAPR guests, hypercalls allow registration of the Virtual Processor
Area (VPA), SLB shadow and dispatch trace log (DTL), each of which allow
for certain communication between the guest and hypervisor. Currently, we
store the addresses of the three areas and the size of the dtl in
CPUPPCState.
From: Ben Herrenschmidt
Currently the lowest "real" irq number for the XICS irq controller (as
opposed to numbers reserved for IPIs and other special purposes) is
hard coded as 16 in two places - in xics_system_init() and in spapr.c.
As well as being generally bad practice, we're going to need t
Currently the XICS irq controller code has a per-irq state structure which
amongst other things includes whether the interrupt is level or message
triggered - this is configured by the platform code, and is not directly
visible to the guest. This leads to a slightly awkward construct at reset
time
From: Michael Ellerman
The kernel will soon be able to service some RTAS calls. However the
choice of tokens will still be up to userspace. To support this have
spapr_rtas_register() return the token that is allocated for an
RTAS call, that allows the calling code to tell the kernel what the
toke
Alex,
Having updated for your latest merge upstream, here's my current
pending set of pseries related patches. Note that 1/16 is an
important bugfix reverting a broken patch of yours: old_portio is not
gone, alas, so we still need the workaround to handle it for in the
pseries PCI code. The rest
From: Jason Baron
This fills out the usb slots on q35, when -usb is passed.
We now have (lspci output):
00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #1 (rev 03)
00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #2 (rev 03)
From: Isaku Yamahata
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jba...@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |1 +
hw/pam.c | 87 +
From: Jason Baron
As pointed out by Andreas Färber this is covered by dec_pci.c.
Signed-off-by: Jason Baron
---
hw/Makefile.objs |2 +-
hw/i21154.c | 113 --
hw/i21154.h |9
3 files changed, 1 insertions(+), 123 deleti
From: Isaku Yamahata
pc q35 based chipset emulator to support pci express natively. Based on
Anthony Liguori's suggestion, the machine name is 'q35-next', with an alias
of 'q35'. At this point, there are no compatibility guarantees. When the
chipset stabilizes more, we will begin to version the m
From: Jason Baron
Cleanup the q35/ich9 license headers.
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 13 +++--
hw/lpc_ich9.c | 32
hw/smbus_ich9.c | 14 --
3 files changed, 23 insertions(+), 36 deletions(-)
diff --git a/hw/acpi_
From: Jason Baron
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron
---
hw/pc.c | 19 +++
hw/pc.h |2 ++
hw/pc_q35.c |7
From: Jan Kiszka
Reviewed-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pc_q35.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index cf0d361..1f31486 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -52,6 +52,
From: Jan Kiszka
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --gi
From: Jason Baron
If -L is specified, and qemu does not find the bios file in , then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jason Baron
---
vl.c | 36 ++
From: Jason Baron
Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
This allows q35 to specify its default disk type. It also allows q35 to
differentiate between ahci and ide disks, such that -drive if=ide does not
result in the creating of an ahci disk. This is importan
From: Jason Baron
The current QEMUMachine definition has a 'use_scsi' field to indicate if a
machine type should use scsi by default. However, Q35 wants to use ahci by
default. Thus, introdue a new field in the QEMUMachine defintion,
default_drive_if.
Please use 'static inline int get_default_dr
From: Jason Baron
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jason Baron
---
hw/pc.c | 24
hw/pc.h |2 ++
hw/pc_piix.c | 25 +
From: Isaku Yamahata
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Reviewed-by: Paolo Bonzini
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pc.c | 15 +++
hw/pc.h
Hi,
Re-base of my previous q35 patches on top of Michael Tsirkin's pci tree.
Qemu bits for q35 support, I'm posting the seabios changes separately. The
patches require '-M q35' and -L 'seabios dir with q35 changes' on the
qemu command line. Hopefully, we can make it the default for x86 at some fu
Device model for Primecell PL330 dma controller.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Kirill Batuzov
Tested-by: Igor Mitsyanko
---
changed from v5:
s/cpu_physical_memory_foo/dma_memory_foo (PMM review)
remove casts of g_new/malloc (PMM review)
s/hw_error/qemu_log_mask for registers r
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_zynq.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index c55dafb..e985e26 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -33,6 +33,10 @@
#define IRQ
These patches add support for the Primcell PL330 DMA controller and add it to
the Xilinx Zynq machine model. Patch 1 is the device model. Patch 2 is the
machine model update.
The Device model was originally contributed by Kirill Batuzov / Samsung, as
indicated by the (C) notice in hw/pl330.c.
If the guest uses a TLBWI instruction for upgrading permissions, we
don't need to flush the extra TLBs. This improve boot time performance
by about 10%.
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
softfloat already has a few constants defined, use them instead of
redefining them in target-mips.
Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and
FP_TO_INT64_OVERFLOW as even if they have the same value, they are
technically different (and defined differently in the MIPS ISA).
R
Only allocate t1 when needed.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 4485a81..c46129d 100644
--- a/ta
Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.
Reviewed-by: Richard Henderson
Sign
Store conditional operations only need local temps in user mode. Fix
the code to use temp local only in user mode, this spares two memory
stores in system mode.
At the same time remove a wrong a wrong copied & pasted comment,
store operations don't have a register destination.
Reviewed-by: Richar
Instead of accessing the flags from the floating point control
register after updating it, read the softfloat flags.
This is just code cleanup and should not change the behaviour.
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c | 118 +++
1
Rework *raise_exception*() functions so that they can be called from
other helpers, passing the return address as an argument.
Use do_raise_exception() function in update_fcr31() to correctly restore
the CPU state after an FPU exception.
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the
address.
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 773c710..cdd6880 100644
--- a/target-mi
This patch series does some bug fixes and code cleanup in the MIPS
target, and then does some optimizations.
Changes v1 -> v2:
- patch 1: new patch
- patch 2: new patch
- patch 5: new patch to address Richard Henders comments
- patch 6: update following patch 5 addition
- patch 7: new pat
When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/target-mips/transla
All changed made,
Thanks,
Peter
On Mon, Oct 29, 2012 at 7:41 PM, Igor Mitsyanko wrote:
> Good day, Peter)
>
>
> On 10/29/2012 10:35 AM, Peter Crosthwaite wrote:
>>
>> Device model for Primecell PL330 dma controller.
>>
>> +
>> +static Property pl330_properties[] = {
>> +/* CR0 */
>> +DEF
All changed made
Thanks,
Peter
On Mon, Oct 29, 2012 at 6:32 PM, Peter Maydell wrote:
> On 29 October 2012 06:35, Peter Crosthwaite
> wrote:
>> Device model for Primecell PL330 dma controller.
>
> A general question -- this is a DMA controller so should it be using
> the DMAContext APIs now? Avi
When the CPU state is restored through retranslation after an exception,
btarget should also be restored.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ed55e26..
The Buildbot has detected a new failure on builder default_mingw32 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_mingw32/builds/420
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_rhel61
Build Reason:
The Buildbot has detected a new failure on builder default_x86_64_rhel61 while
building qemu.
Full details are available at:
http://buildbot.b1-systems.de/qemu/builders/default_x86_64_rhel61/builds/420
Buildbot URL: http://buildbot.b1-systems.de/qemu/
Buildslave for this Build: kraxel_rhel61
B
Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 91 ---
1 fil
The result of a division by 0, or a division of INT_MIN by -1 in the
signed case, is unpredictable. Just replace 0 by 1 in that case so that
it doesn't trigger a floating point exception on the host.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 85 +--
From: Aurelien Jarno
The TCG arm backend considers likely that the offset to the TLB
entries does not exceed 12 bits for mem_index = 0. In practice this is
not true for at least the MIPS target.
The current patch fixes that by loading the bits 23-12 with a separate
instruction, and using loads w
From: Aurelien Jarno
The bswap16 TCG opcode assumes that the high bytes of the temp equal
to 0 before calling it. The ARM backend implementation takes this
assumption to slightly optimize the generated code.
The same implementation is called for implementing the cross-endian
qemu_st16 opcode, wh
From: Aurelien Jarno
On an ARM host, the registers definitions from cpu.h clash
with /usr/include/sys/ucontext.h. As there are unused, just remove
them.
Cc: Jia Liu
Cc: qemu-sta...@nongnu.org
Signed-off-by: Aurelien Jarno
---
target-openrisc/cpu.h | 18 --
1 file changed, 18
From: Aurelien Jarno
This patch series fixes the TCG arm backend for the MIPS target, as well
as for big endian targets when not using the ARMv6+ instructions set.
The corresponding patches are candidate for a stable release.
--
Changes v1 -> v2:
- patch 1:
- added an assert to make sure the
Avoid the branches in movn/movz implementation and replace them with
movcond. Also update a wrong command.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a
load/store microMIPS helpers are reinventing the wheel. Call do_lw,
do_ll, do_sw and do_sl instead of using a macro calling the cpu_*
load/store functions.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c | 73 ++-
Instead of clearing the softfloat exception flags before each floating
point instruction, reset them to 0 in update_fcr31() when an exception
is detected.
Signed-off-by: Aurelien Jarno
---
target-mips/op_helper.c | 73 +++
1 file changed, 10 insertio
For each FPU instruction that can trigger an FPU exception, to call
call update_fcr31() after.
Remove the manual NaN assignment in case of float to float operation, as
softfloat is already taking care of that. However for float to int
operation, the value has to be changed to the MIPS one. In the
Load/store from helpers should be avoided as they are quite
inefficient. Rewrite unaligned loads instructions using TCG and
aligned loads. The number of actual loads operations to implement
an unaligned load instruction is reduced from up to 8 to 1.
Note: As we can't rely on shift by 32 or 64 unde
Add a pickNaNMulAdd function for MIPS, implementing NaN propagation
rules for MIPS fused multiply-add instructions.
Cc: Peter Maydell
Signed-off-by: Aurelien Jarno
---
fpu/softfloat-specialize.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/fpu/softfloat-spe
Use the deposit op instead of and hardcoded bit field insertion. It
allows the host to emit the corresponding instruction if available.
At the same time remove the (lsb > msb) test. The MIPS64R2 instruction
set manual says "Because of the instruction format, lsb can never be
greater than msb, so t
On Mon, Oct 29, 2012 at 07:40:17PM +0100, Alexander Graf wrote:
> Hi Blue / Aurelien,
>
> This is my current patch queue for s390. Please pull.
>
> Alex
>
>
> The following changes since commit b308c82cbda44e138ef990af64d44a5613c16092:
> Avi Kivity (1):
> pci: avoid destroying bridge
Il 29/10/2012 18:32, Juan Quintela ha scritto:
>> > New users can't "just add socket_set_nonblock()". They'd have to add it
>> > right where you deleted it: between qemu_socket() and connect(). Else
>> > the connect() is blocking.
> Grrr.
>
> So, is there any way to make a connection that is non
Avi Kivity writes:
> The memory core drops regions that are hidden by another region (for example,
> during BAR sizing), but it doesn't do so correctly if the lower address of the
> existing range is below the lower address of the new range.
>
> Example (qemu-system-mips -M malta -kernel vmlinux-
"Michael S. Tsirkin" writes:
> The following changes since commit d262cb02861dd33375c08fc798930653b14769e9:
>
> Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf (2012-10-29
> 14:56:17 +0100)
>
> are available in the git repository at:
Pulled. Thanks.
Regards,
Anthony Liguori
On Fri, Oct 12, 2012 at 03:56:05PM -0400, Don Slutz wrote:
> Also known as Paravirtualization CPUIDs.
>
> This is primarily done so that the guest will think it is running
> under vmware when hypervisor-vendor=vmware is specified as a
> property of a cpu.
>
> Patches 1 to 3 define new cpu propert
On Wed, Oct 24, 2012 at 07:44:04PM -0200, Eduardo Habkost wrote:
> This depends on a previous series I have submitted:
> Subject: [QEMU PATCH 00/15] QEMU KVM_GET_SUPPORTED_CPUID cleanups and fixes
> Message-Id: <1349383747-19383-1-git-send-email-ehabk...@redhat.com>
> http://article.gmane.org
On Mon, Oct 29, 2012 at 06:53:14PM +0100, Paolo Bonzini wrote:
> Known-good commit: 8473f377393219390ea6f2d8d450a2b054bb823e
> Known-bad commit: d262cb02861dd33375c08fc798930653b14769e9
>
> i386-softmmu seems to work. I may try to bisect it tomorrow, but I'd be
> glad if somebody else beats me.
Gerd Hoffmann writes:
> Hi,
>
> Here comes the usb patch queue. Nothing big standing out. Tons of
> cleanups and small bug fixes. Some performance improvements too.
> Some patches preparing the usb core for the upcoming input pipelining
> bits.
>
> please pull,
> Gerd
>
Pulled. Thanks.
R
Kevin Wolf writes:
> The following changes since commit a8170e5e97ad17ca169c64ba87ae2f53850dab4c:
>
> Rename target_phys_addr_t to hwaddr (2012-10-23 08:58:25 -0500)
>
> are available in the git repository at:
>
> git://repo.or.cz/qemu/kevin.git for-anthony
>
Pulled. Thanks.
Regards,
Antho
From: Heinz Graalfs
This code adds console support by implementing SCLP's ASCII Console
Data event. This is the same console as LPARs ASCII console or z/VMs
sysascii.
The console can be specified manually with something like
-chardev stdio,id=charconsole0 -device
sclpconsole,chardev=charconsol
This removes the dependency of cutils.c on iov.c, and lets us remove
iov.o from several builds.
Signed-off-by: Paolo Bonzini
---
Makefile | 2 +-
Makefile.objs | 4 +--
cutils.c | 103 -
iov.c | 103 +++
From: Heinz Graalfs
This implements the sclp signal quiesce event via the SCLP Event
Facility.
This allows to gracefully shutdown a guest by using system_powerdown
notifiers. It creates a service interrupt that will trigger a
Read Event Data command from the guest. This code will then add an
even
From: Heinz Graalfs
Correct sys_perf_event_open syscall number for s390 architecture
- the hardcoded syscall number 298 is for x86 but should
be different for other architectures.
In case we figure out via /proc/cpuinfo that we are running
on s390 the appropriate syscall number
On 28.10.2012, at 12:04, Blue Swirl wrote:
> Add missing 'static' qualifiers.
>
> Signed-off-by: Blue Swirl
Acked-by: Alexander Graf
Alex
On 28.10.2012, at 12:04, Blue Swirl wrote:
> Signed-off-by: Blue Swirl
Acked-by: Alexander Graf
Alex
> ---
> target-ppc/cpu.h|6 --
> target-ppc/mmu_helper.c | 11 ++-
> 2 files changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/
Hi Blue / Aurelien,
This is my current patch queue for s390. Please pull.
Alex
The following changes since commit b308c82cbda44e138ef990af64d44a5613c16092:
Avi Kivity (1):
pci: avoid destroying bridge address space windows in a transaction
are available in the git repository at:
Signed-off-by: Paolo Bonzini
---
qemu-tool.c | 2 +-
1 file modificato, 1 inserzione(+). 1 rimozione(-)
diff --git a/qemu-tool.c b/qemu-tool.c
index 28a4e8d..b46631e 100644
--- a/qemu-tool.c
+++ b/qemu-tool.c
@@ -70,7 +70,7 @@ void monitor_protocol_event(MonitorEvent event, QObject *data)
int
From: Heinz Graalfs
This adds a more generic infrastructure for handling Service-Call
requests on s390. Currently we only support a small subset of Read
SCP Info directly in target-s390x. This patch provides the base
infrastructure for supporting more commands and moves Read SCP
Info.
In the futu
Signed-off-by: Paolo Bonzini
---
cutils.c | 5 -
osdep.c | 30 ++
qemu-common.h | 1 -
qemu-tool.c | 20
qemu-user.c | 20
5 file modificati, 30 inserzioni(+), 46 rimozioni(-)
diff --git a/cutils.c b/cutil
Signed-off-by: Paolo Bonzini
---
Makefile | 6 +++---
Makefile.objs | 5 ++---
tests/Makefile | 4 ++--
3 file modificati, 7 inserzioni(+), 8 rimozioni(-)
diff --git a/Makefile b/Makefile
index e489583..2ba981c 100644
--- a/Makefile
+++ b/Makefile
@@ -171,7 +171,7 @@ endif
qemu-img.o: qe
From: Christian Borntraeger
Newer kernels provide the guest registers in kvm_run. Lets use
those if available (i.e. the capability is set). This avoids
ioctls on cpu_synchronize_state making intercepts faster.
In addition, we have now the prefix register, the access registers
the control registe
From: Heinz Graalfs
Several SCLP features are considered to be events. Those events don't
provide SCLP commands on their own, instead they are all based on
Read Event Data, Write Event Data, Write Event Mask and the service
interrupt. Follow-on patches will provide SCLP's Signal Quiesce (via
syst
When using -initrd in the virtio machine, we need to indicate the initrd
start and size inside the kernel image. These parameters need to be stored
in native endianness.
Signed-off-by: Alexander Graf
Acked-by: Richard Henderson
Acked-by: Christian Borntraeger
---
hw/s390-virtio.c |4 ++--
Hi Blue / Aurelien,
This is my current patch queue for s390. Please pull.
Alex
The following changes since commit b308c82cbda44e138ef990af64d44a5613c16092:
Avi Kivity (1):
pci: avoid destroying bridge address space windows in a transaction
are available in the git repository at:
When using -initrd in the virtio machine, we need to indicate the initrd
start and size inside the kernel image. These parameters need to be stored
in native endianness.
Signed-off-by: Alexander Graf
Acked-by: Richard Henderson
Acked-by: Christian Borntraeger
---
hw/s390-virtio.c |4 ++--
This is simpler and more portable.
Signed-off-by: Paolo Bonzini
---
arch_init.h | 2 +-
compiler.h | 11 ---
qmp.c | 3 ++-
3 file modificati, 7 inserzioni(+), 9 rimozioni(-)
diff --git a/arch_init.h b/arch_init.h
index d9c572a..5fc780c 100644
--- a/arch_init.h
+++ b/arch_init.
Signed-off-by: Paolo Bonzini
---
qemu-timer.c | 12 +---
1 file modificato, 9 inserzioni(+), 3 rimozioni(-)
diff --git a/qemu-timer.c b/qemu-timer.c
index ede84ff..f3426c9 100644
--- a/qemu-timer.c
+++ b/qemu-timer.c
@@ -430,9 +430,11 @@ void qemu_unregister_clock_reset_notifier(QEMUCloc
Signed-off-by: Paolo Bonzini
---
main-loop.c | 5 -
main-loop.h | 10 --
qemu-tool.c | 7 ---
vl.c| 5 -
4 file modificati, 4 inserzioni(+), 23 rimozioni(-)
diff --git a/main-loop.c b/main-loop.c
index eb3b6e6..baefe41 100644
--- a/main-loop.c
+++ b/main-loop.c
@@
Signed-off-by: Paolo Bonzini
---
oslib-win32.c | 5 +
1 file modificato, 5 inserzioni(+)
diff --git a/oslib-win32.c b/oslib-win32.c
index 51b33e8..9ca83df 100644
--- a/oslib-win32.c
+++ b/oslib-win32.c
@@ -150,3 +150,8 @@ int qemu_get_thread_id(void)
{
return GetCurrentThreadId();
}
+
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