[Qemu-devel] [PATCH v2 01/19] target-mips: correctly restore btarget upon exception

[Aurelien Jarno]

When the CPU state is restored through retranslation after an exception,
btarget should also be restored.

Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
 target-mips/translate.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index ed55e26..3cf4ca1 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -578,6 +578,7 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
 static TCGv_i64 fpu_f64[32];
 
 static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
+static target_ulong gen_opc_btarget[OPC_BUF_SIZE];
 
 #include "gen-icount.h"
 
@@ -12859,6 +12860,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, 
TranslationBlock *tb,
             }
             gen_opc_pc[lj] = ctx.pc;
             gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
+            gen_opc_btarget[lj] = ctx.btarget;
             gen_opc_instr_start[lj] = 1;
             gen_opc_icount[lj] = num_insns;
         }
@@ -13274,4 +13276,13 @@ void restore_state_to_opc(CPUMIPSState *env, 
TranslationBlock *tb, int pc_pos)
     env->active_tc.PC = gen_opc_pc[pc_pos];
     env->hflags &= ~MIPS_HFLAG_BMASK;
     env->hflags |= gen_opc_hflags[pc_pos];
+    switch (env->hflags & MIPS_HFLAG_BMASK_BASE) {
+    case MIPS_HFLAG_BR:
+        break;
+    case MIPS_HFLAG_BC:
+    case MIPS_HFLAG_BL:
+    case MIPS_HFLAG_B:
+        env->btarget = gen_opc_btarget[pc_pos];
+        break;
+    }
 }
-- 
1.7.10.4